Validation status
Generated 02-Nov-2026 14:11:07 · 110 test cases in 13 peripherals
Overall progress
Test cases
110
P135P232No priority43
Passed
55
P115P210No priority30
Failed
3
P10P20No priority3
Remaining
13
P13P210No priority0
Needs Attention
39
P117P212No priority10
Passed 55 + Failed 3 + Remaining 13 + Needs Attention 39 = 110 test cases
Bench time (estimates)
| Tests | Execution (min – max) | Setup (min – max) | Total (min – max) | Estimated | |
|---|---|---|---|---|---|
| All tests | 110 | tbd | tbd | tbd | 1 of 110 tests 0 of 14 setups |
| Not passed | 55 | tbd | tbd | tbd | 0 of 55 tests 0 of 12 setups |
PASSFAILIn developmentNot implemented
All peripherals
| Peripheral | Tests | Not implemented | In development | PASS | FAIL | P1 passed | Last run |
|---|---|---|---|---|---|---|---|
| ARM_CORE | 6 | 0 | 0 | 6 | 0 | - | 10-Sep-2026 11:16:42 |
| GPIO | 4 | 0 | 0 | 2 | 2 | - | 17-Sep-2026 15:11:45 |
| GPT | 44 | 5 | 2 | 37 | 0 | 16 / 16 | 21-Sep-2026 12:22:28 |
| I2C | 1 | 0 | 0 | 1 | 0 | - | 01-Sep-2026 11:40:12 |
| NVMC | 4 | 0 | 1 | 3 | 0 | - | 10-Sep-2026 11:16:30 |
| PWM | 12 | 0 | 0 | 12 | 0 | - | 23-Sep-2026 15:49:36 |
| SARADC | 4 | 0 | 3 | 1 | 0 | - | 02-Sep-2026 19:15:44 |
| SRAM | 3 | 0 | 0 | 3 | 0 | - | 17-Sep-2026 16:52:00 |
| SYSTICK | 1 | 0 | 0 | 1 | 0 | - | 23-Sep-2026 15:49:00 |
| TRGRTR | 10 | 8 | 1 | 1 | 0 | 1 / 8 | 03-Sep-2026 17:22:32 |
| UART | 16 | 6 | 3 | 7 | 0 | 7 / 11 | 07-Sep-2026 19:28:27 |
| VAAK SoC | 1 | 0 | 1 | 0 | 0 | - | 22-Oct-2026 13:26:30 |
| WDT | 4 | 0 | 2 | 1 | 1 | - | 07-Sep-2026 19:18:02 |
Needs Attention
Not PASSED, By Owner
| Owner | Failed | Needs Attention | Remaining | Total not passed | Peripherals |
|---|---|---|---|---|---|
| Chandana | 0 | 18 | 5 | 23 | GPT 23 |
| Jyeshta | 0 | 2 | 1 | 3 | UART 3 |
| unassigned | 3 | 19 | 7 | 29 | GPIO 2 · GPT 3 · NVMC 1 · SARADC 3 · TRGRTR 10 · UART 6 · VAAK SoC 1 · WDT 3 |
Unattended runs (Jenkins)
Ready and auto: 14 tests on 7 setups · execution tbd (1 of 14 tests estimated)
GPT0_TOUT_LATC_GPT_0011execution tbd (0 of 1 tests estimated)
GPT1_TOUT_LATC_GPT_0014execution tbd (0 of 1 tests estimated)
GPT2_TOUT_LATC_GPT_0017execution tbd (0 of 1 tests estimated)
GPT3_TOUT_LATC_GPT_0020execution tbd (0 of 1 tests estimated)
UART_LOOP_IOSET0TC_UART_0003, TC_UART_0007execution tbd (0 of 2 tests estimated)
UART_LOOP_IOSET1TC_UART_0004execution tbd (0 of 1 tests estimated)
no wiringTC_GPT_0001, TC_GPT_0002, TC_GPT_0003, TC_GPT_0004, TC_TRGRTR_0002, TC_UART_0001, TC_UART_0002execution tbd (1 of 7 tests estimated)
Also ready: 2 host and 30 manual tests.