| TC_WDT_0001 | WDT_REG_RW - Verify default register values after reset
- Pattern write/read verification on RW registers
- Read-only register validation for STS
- OTP bits [3:1] validation in CTRL register
- Reserved bits write protection check
- Random read/write validation on registers
- Invalid address access generates PSLVERR
- Byte, half-word, and word access verification (hsize/pstrb)
- Multi-reset sequence validation (C_RESET1 to C_RESET4)
| - | unassigned | PASS 1/1 | 07-Sep-2026 19:17:50 | - - execution tbd |
| TC_WDT_0002 | WDT_GEN_OF_INTERNAL_RESET - The test intent is to check the Generation of Internal Reset by WDOG timer when WDTON in set HIthe test intent is to check if the Counter value of the WDOG timer is reset and WDT_OUT is generated
- After a specific value (0xAD1E) is written on WDTC register outside the window when CWTEN is set HIGH or LOW.
- After a specific value (0xAD1E) is written on WDTC register within the window just after reset.
- When a value other than the specified value (0xAD1E) is written on WDTC register.
- When Overflow has been reached.
| - | unassigned | In development 0/1 | 25-Aug-2026 15:29:48 | - - execution tbd |
| TC_WDT_0003 | WDT_GEN_MCU_RESET - the test intent is to check if a MCU reset is generated by the CRM module when WDT_OUT is received from WDT.
- Further check if system reset is not generated by the CRM and check default values of the registers in the WDT or other blocks.
| - | unassigned | FAIL 0/1 | 07-Sep-2026 19:18:02 | - - execution tbd |
| TC_WDT_0004 | WDT_LPM_WAKEUP_REQ - The test intent is to check the WDOGT functionality in different modes (Low Power mode are decided based on the input signal lpmsts[1:0]) by using bits CTRLBITS[1:0]:-
- 0x0: WDOG is on only in RUN Mode
- 0x1: WDOG is on only in RUN and Idle Mode
- 0x2: WDOG is on except in Deep Sleep Mode
- 0x3: WDOG is always on
| - | unassigned | In development 0/1 | 25-Aug-2026 15:29:19 | - - execution tbd |