GPT

44 test cases · GPT0, GPT1, GPT2, GPT3 · silicon 1.0 · generated 02-Nov-2026 14:11:07

PASS 37In development 2Not implemented 5

P1 · customer sample gate16 of 16 passed · 0 not passed

P2 · full validation20 of 25 passed · 5 not passed

No priority set1 of 3 passed · 2 not passed

Bench time (estimates)

	Tests	Execution (min – max)	Setup (min – max)	Total (min – max)	Estimated
All tests	44	tbd	tbd	tbd	0 of 44 tests 0 of 5 setups
Not passed	26	tbd	tbd	tbd	0 of 26 tests 0 of 5 setups

Feature coverage · 31 features · 16 verified · 0 failing · 15 open

Feature	Covered by	Feature status
Register reset values and R/W access	0001 0002 0003 0004	PASS
Soft reset (SRST) restores reset values	0001 0002 0003 0004	PASS
PWM mode at 50 percent duty	0005 0006 0007 0008	PASS
INTA, INTB, EXPA and EXPB interrupts	0005 0006 0007 0008 0026 0027 0028 0029	PASS
Single pulse mode	0009 0012 0015 0018	PASS
Single pulse stopped early by clearing SPS	0010 0013 0016 0019	PASS
Single pulse mode with CNTRA 0 to 3	0011 0014 0017 0020	PASS
GPT0 GPT1 Cascade Test	0021 0021 0021	PASS
Standard timer mode on FCLK	0022 0023 0024 0025	PASS
INTB and EXPB interrupts in standard timer mode	0022 0023 0024 0025 0030 0031 0032 0033	PASS
Compare match mode	0026 0027 0028 0029	PASS
Compare ratios 25/50/75 percent and minimum and maximum counts	0026 0027 0028 0029	PASS
CNTRA and CNTRB update while running (shadow load)	0026 0027 0028 0029	PASS
Standard timer mode on AUXCLK from the LF oscillator	0030 0031 0032 0033	PASS
GPT interrupt wakes the CPU from idle, sleep and deep sleep	0034 0035 0036 0037	PASS
CNTRA update while the CPU is in low-power mode	0034 0035 0036 0037	PASS
Clock source switch between FCLK and AUXCLK while running	0038	Not implemented
Glitch-free mux bypass (GFB)	0038	Not implemented
Prescaler and divider range	0038	Not implemented
Output polarity invert (INV)	0039	Not implemented
Output enable (TOEN)	0039	Not implemented
Pause and resume (PS)	0039	Not implemented
COUNT register read while running	0040	Not implemented
BUSY and SYNBUSY status	0040	Not implemented
Trigger input starts the timer (gpt_trg_in)	0041	Not implemented
Trigger output at each TOUT toggle (gpt_trg_out)	0041	Not implemented
Trigger output while the CPU is in low-power mode	0041	Not implemented
Interrupt enable bits gate each source	0042	Not implemented
Status bits clear only on write 1	0042	Not implemented
Interrupt sources share one IRQ line	0042	Not implemented
No interrupt for CNTRA and CNTRB below 5	0042	Not implemented

Test cases

44 of 44 shown

Priority

Status

Test case	Name and test description	Priority	Owner	Status	Last run	Run mode · setup · execution
TC_GPT_0001	GPT0_REG_RW Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18 Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18 Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL	P1	Chandana	PASS 1/1	31-Aug-2026 12:40:17	auto no wiring execution tbd
TC_GPT_0002	GPT1_REG_RW Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18 Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18 Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL	P1	Chandana	PASS 1/1	31-Aug-2026 13:16:22	auto no wiring execution tbd
TC_GPT_0003	GPT2_REG_RW Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18 Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18 Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL	P1	Chandana	PASS 1/1	31-Aug-2026 13:51:15	auto no wiring execution tbd
TC_GPT_0004	GPT3_REG_RW Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18 Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18 Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL	P1	Chandana	PASS 1/1	31-Aug-2026 13:56:12	auto no wiring execution tbd
TC_GPT_0005	GPT0_PWM_MODE Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10 TOUT on GPIO3 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5	P2	Chandana	PASS 1/1	31-Aug-2026 13:03:52	manual GPT0_TOUT_LA execution tbd
TC_GPT_0006	GPT1_PWM_MODE Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10 TOUT on GPIO4 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5	P2	Chandana	PASS 1/1	31-Aug-2026 13:16:09	manual GPT1_TOUT_LA execution tbd
TC_GPT_0007	GPT2_PWM_MODE Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10 TOUT on GPIO5 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5	P2	Chandana	PASS 1/1	31-Aug-2026 13:50:22	manual GPT2_TOUT_LA execution tbd
TC_GPT_0008	GPT3_PWM_MODE Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10 TOUT on GPIO6 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5	P2	Chandana	PASS 1/1	31-Aug-2026 13:56:06	manual GPT3_TOUT_LA execution tbd
TC_GPT_0009	GPT0_SINGLE_PULSE_MODE Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22) TOUT pulse on GPIO3 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for two INTA interrupts and then checks that exactly two occurred	P2	Chandana	PASS 1/1	31-Aug-2026 13:04:25	manual GPT0_TOUT_LA execution tbd
TC_GPT_0010	GPT0_SINGLE_PULSE_MODE_CLEAR_SPS Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts) The GPT is disabled and re-enabled for a second pulse After the third INTA the code clears SPS part-way through the pulse	P2	Chandana	PASS 1/1	31-Aug-2026 13:04:02	manual GPT0_TOUT_LA execution tbd
TC_GPT_0011	GPT0_SINGLE_PULSE_MODE_CNTRA Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2) TOUT on GPIO3 for observation	P2	Chandana	PASS 1/1	31-Aug-2026 13:04:12	auto GPT0_TOUT_LA execution tbd
TC_GPT_0012	GPT1_SINGLE_PULSE_MODE Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22) TOUT pulse on GPIO4 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for two INTA interrupts and then checks that exactly two occurred	P2	Chandana	PASS 1/1	31-Aug-2026 13:26:02	manual GPT1_TOUT_LA execution tbd
TC_GPT_0013	GPT1_SINGLE_PULSE_MODE_CLEAR_SPS Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts) The GPT is disabled and re-enabled for a second pulse After the third INTA the code clears SPS part-way through the pulse	P2	Chandana	PASS 1/1	31-Aug-2026 13:24:20	manual GPT1_TOUT_LA execution tbd
TC_GPT_0014	GPT1_SINGLE_PULSE_MODE_CNTRA Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2) TOUT on GPIO4 for observation	P2	Chandana	PASS 1/1	31-Aug-2026 13:25:45	auto GPT1_TOUT_LA execution tbd
TC_GPT_0015	GPT2_SINGLE_PULSE_MODE Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22) TOUT pulse on GPIO5 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for two INTA interrupts and then checks that exactly two occurred	P2	Chandana	PASS 1/1	31-Aug-2026 13:53:39	manual GPT2_TOUT_LA execution tbd
TC_GPT_0016	GPT2_SINGLE_PULSE_MODE_CLEAR_SPS Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts) The GPT is disabled and re-enabled for a second pulse After the third INTA the code clears SPS part-way through the pulse	P2	Chandana	PASS 1/1	31-Aug-2026 13:51:26	manual GPT2_TOUT_LA execution tbd
TC_GPT_0017	GPT2_SINGLE_PULSE_MODE_CNTRA Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2) TOUT on GPIO5 for observation	P2	Chandana	PASS 1/1	31-Aug-2026 13:52:50	auto GPT2_TOUT_LA execution tbd
TC_GPT_0018	GPT3_SINGLE_PULSE_MODE Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22) TOUT pulse on GPIO6 and an interrupt marker pulse on GPIO14 for each GPT interrupt The code waits for two INTA interrupts and then checks that exactly two occurred	P2	Chandana	PASS 1/1	31-Aug-2026 13:56:53	manual GPT3_TOUT_LA execution tbd
TC_GPT_0019	GPT3_SINGLE_PULSE_MODE_CLEAR_SPS Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts) The GPT is disabled and re-enabled for a second pulse After the third INTA the code clears SPS part-way through the pulse	P2	Chandana	PASS 1/1	31-Aug-2026 13:56:20	manual GPT3_TOUT_LA execution tbd
TC_GPT_0020	GPT3_SINGLE_PULSE_MODE_CNTRA Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2) TOUT on GPIO6 for observation	P2	Chandana	PASS 1/1	31-Aug-2026 13:56:28	auto GPT3_TOUT_LA execution tbd
TC_GPT_0021	GPT0_GPT1_Cascade_test GPT cascading test,Providing tout of gpt0 as clock to gpt1 as aux_clk & observing the gpt1 tout behaviour , considering the test as 32bit counter GPIO4 PAD used as muxing to observe tout.	-	unassigned	In development	-	- - execution tbd
TC_GPT_0021	GPT0_GPT1_Cascade_test GPT cascading test,Providing tout of gpt0 as clock to gpt1 as aux_clk & observing the gpt1 tout behaviour , considering the test as 32bit counter GPIO4 PAD used as muxing to observe tout.	-	unassigned	In development	-	- - execution tbd
TC_GPT_0021	GPT0_GPT1_Cascade_test GPT cascading test,Providing tout of gpt0 as clock to gpt1 as aux_clk & observing the gpt1 tout behaviour , considering the test as 32bit counter GPIO4 PAD used as muxing to observe tout.	-	unassigned	PASS 1/1	02-Sep-2026 19:16:07	- - execution tbd
TC_GPT_0022	GPT0_STD_TIMER_MODE Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count) TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT	P1	Chandana	PASS 1/1	31-Aug-2026 13:04:49	manual GPT0_TOUT_LA execution tbd
TC_GPT_0023	GPT1_STD_TIMER_MODE Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count) TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT	P1	Chandana	PASS 1/1	31-Aug-2026 13:27:00	manual GPT1_TOUT_LA execution tbd
TC_GPT_0024	GPT2_STD_TIMER_MODE Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count) TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT	P1	Chandana	PASS 1/1	31-Aug-2026 13:54:21	manual GPT2_TOUT_LA execution tbd
TC_GPT_0025	GPT3_STD_TIMER_MODE Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count) TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT	P1	Chandana	PASS 1/1	31-Aug-2026 13:57:55	manual GPT3_TOUT_LA execution tbd
TC_GPT_0026	GPT1_COMPARE_MATCH_MODE Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2 Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8) Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB TOUT on GPIO4 and an interrupt marker pulse on GPIO14 for each GPT interrupt	P2	Chandana	PASS 1/1	31-Aug-2026 13:15:49	manual GPT1_TOUT_LA execution tbd
TC_GPT_0027	GPT2_COMPARE_MATCH_MODE Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2 Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8) Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB TOUT on GPIO5 and an interrupt marker pulse on GPIO14 for each GPT interrupt	P2	Chandana	PASS 1/1	31-Aug-2026 13:50:03	manual GPT2_TOUT_LA execution tbd
TC_GPT_0028	GPT0_COMPARE_MATCH_MODE Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2 Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8) Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB TOUT on GPIO3 and an interrupt marker pulse on GPIO14 for each GPT interrupt	P2	Chandana	PASS 1/1	31-Aug-2026 13:03:35	manual GPT0_TOUT_LA execution tbd
TC_GPT_0029	GPT3_COMPARE_MATCH_MODE Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2 Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8) Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB TOUT on GPIO6 and an interrupt marker pulse on GPIO14 for each GPT interrupt	P2	Chandana	PASS 1/1	31-Aug-2026 13:55:53	manual GPT3_TOUT_LA execution tbd
TC_GPT_0030	GPT0_STD_TIMER_MODE_LFOSC Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts	P1	Chandana	PASS 1/1	31-Aug-2026 13:04:35	manual GPT0_TOUT_LA execution tbd
TC_GPT_0031	GPT1_STD_TIMER_MODE_LFOSC Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts	P1	Chandana	PASS 1/1	31-Aug-2026 13:26:45	manual GPT1_TOUT_LA execution tbd
TC_GPT_0032	GPT2_STD_TIMER_MODE_LFOSC Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts	P1	Chandana	PASS 1/1	31-Aug-2026 13:54:00	manual GPT2_TOUT_LA execution tbd
TC_GPT_0033	GPT3_STD_TIMER_MODE_LFOSC Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms) For each value the code waits for INTB, EXPB and at least 7 INTB interrupts	P1	Chandana	PASS 1/1	31-Aug-2026 13:57:23	manual GPT3_TOUT_LA execution tbd
TC_GPT_0034	GPT3_LPM_MODE GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80 After the first INTB the CPU enters idle and waits for interrupt After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt The test ends after 8 INTB interrupts	P1	Chandana	PASS 1/1	21-Sep-2026 12:22:28	manual GPT3_TOUT_LA execution tbd
TC_GPT_0035	GPT0_LPM_MODE GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80 After the first INTB the CPU enters idle and waits for interrupt After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt The test ends after 8 INTB interrupts	P1	Chandana	PASS 1/1	21-Sep-2026 12:20:29	manual GPT0_TOUT_LA execution tbd
TC_GPT_0036	GPT1_LPM_MODE GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80 After the first INTB the CPU enters idle and waits for interrupt After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt The test ends after 8 INTB interrupts	P1	Chandana	PASS 1/1	21-Sep-2026 12:21:50	manual GPT1_TOUT_LA execution tbd
TC_GPT_0037	GPT2_LPM_MODE GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80 After the first INTB the CPU enters idle and waits for interrupt After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt The test ends after 8 INTB interrupts	P1	Chandana	PASS 1/1	21-Sep-2026 12:22:06	manual GPT2_TOUT_LA execution tbd
TC_GPT_0038	GPT_CLOCK_SELECT Switch CLKSEL from FCLK to AUXCLK and back while the GPT runs; the switch takes effect after two clock cycles Repeat the switch with GFB=1 (glitch-free mux bypassed) Run with prescaler /1 and /8, and with DIV 0 (/2) and DIV 255 (/512) Measure the INTB period with SysTick for each case and compare it with the value computed from the clock settings	P2	Chandana	Not implemented	-	auto no wiring execution tbd
TC_GPT_0039	GPT_OUTPUT_CONTROL Run PWM mode with INV=0 and then INV=1 and compare the TOUT waveforms Run with TOEN=0 and check that the pad stays idle while the counter runs (COUNT keeps changing) Set PS while running, check that COUNT holds, then clear PS and check that counting resumes	P2	Chandana	Not implemented	-	manual GPT_TOUT_ALL_LA execution tbd
TC_GPT_0040	GPT_COUNT_AND_STATUS Read COUNT while the GPT runs, repeating each read until two reads match (reference manual 14.8.1) Check that COUNT increases between reads and wraps at CNTRB Check that BUSY is set when GPTEN is set, and that a re-enable after disable takes effect only after BUSY clears Check SYNBUSY around a register write	P2	Chandana	Not implemented	-	auto no wiring execution tbd
TC_GPT_0041	GPT_TRIGGER_IN_OUT Route a trigger source to gpt_trg_in through the trigger router and check that GPTEN is set by the pulse Route gpt_trg_out to another block through the trigger router and count one pulse per TOUT toggle Repeat the trigger-out check with the CPU in sleep, without waking the CPU	P2	Chandana	Not implemented	-	auto no wiring execution tbd
TC_GPT_0042	GPT_INTERRUPT_ENABLES Enable INTAEN, INTBEN, EXPAEN and EXPBEN one at a time and check that only the enabled source raises the IRQ Check that the status bits still set when their enable bit is clear Write 1 to one status bit and check that only that bit clears Raise several sources together and check that they arrive on the single GPT IRQ line Run with CNTRA and CNTRB below 5 and check that TOUT runs but no interrupt is raised (reference manual 14.8.1)	P2	Chandana	Not implemented	-	auto no wiring execution tbd

TC_GPT_0001 · GPT0_REG_RW

PASS1/1

P1readyowner Chandanarun autono wiringexecution tbd

Last run31-Aug-2026 12:40:17

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18
Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18
Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues
Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues
Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL

Pass / fail criteria

All register reads match the expected values after masking (reset, pattern, random, all access sizes)
Each invalid access raises the expected HardFault and the test resumes after reset
Final TEST_RESULT is [[PASS]] with no [[FAIL]] events

Hardware connection

No external connections apart from the logger

Features and configuration

1 result

TC_GPT_0002 · GPT1_REG_RW

PASS1/1

P1readyowner Chandanarun autono wiringexecution tbd

Last run31-Aug-2026 13:16:22

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18
Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18
Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues
Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues
Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL

Pass / fail criteria

All register reads match the expected values after masking (reset, pattern, random, all access sizes)
Each invalid access raises the expected HardFault and the test resumes after reset
Final TEST_RESULT is [[PASS]] with no [[FAIL]] events

Hardware connection

No external connections apart from the logger

Features and configuration

1 result

TC_GPT_0003 · GPT2_REG_RW

PASS1/1

P1readyowner Chandanarun autono wiringexecution tbd

Last run31-Aug-2026 13:51:15

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18
Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18
Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues
Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues
Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL

Pass / fail criteria

All register reads match the expected values after masking (reset, pattern, random, all access sizes)
Each invalid access raises the expected HardFault and the test resumes after reset
Final TEST_RESULT is [[PASS]] with no [[FAIL]] events

Hardware connection

No external connections apart from the logger

Features and configuration

1 result

TC_GPT_0004 · GPT3_REG_RW

PASS1/1

P1readyowner Chandanarun autono wiringexecution tbd

Last run31-Aug-2026 13:56:12

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Soft reset through CTRL.SRST, then check reset values of CTRL, STS, CNTRA, CNTRB, COUNT and the registers at offsets 0x14 and 0x18
Walking 1s, 0s, 5s and As patterns and random data write/read on CTRL, STS, CNTRA, CNTRB and offsets 0x14 and 0x18
Write to COUNT is expected to raise a HardFault (COUNT is read-only); the test resets and continues
Write to a random unmapped address in the GPT block is expected to raise a HardFault; the test resets and continues
Byte, half-word and word accesses (hsize/pstrb check), plus three custom data words on CTRL

Pass / fail criteria

All register reads match the expected values after masking (reset, pattern, random, all access sizes)
Each invalid access raises the expected HardFault and the test resumes after reset
Final TEST_RESULT is [[PASS]] with no [[FAIL]] events

Hardware connection

No external connections apart from the logger

Features and configuration

1 result

TC_GPT_0005 · GPT0_PWM_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:03:52

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10
TOUT on GPIO3 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5

Pass / fail criteria

TOUT duty cycle is 50 percent and the period follows CNTRB, checked on the logic-analyser capture (result_output_img)
Interrupt counts are INTA 5, INTB 6, EXPA 4 and EXPB 5
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

PWM mode at 50 percent dutyINTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0006 · GPT1_PWM_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:16:09

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10
TOUT on GPIO4 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5

Pass / fail criteria

TOUT duty cycle is 50 percent and the period follows CNTRB, checked on the logic-analyser capture (result_output_img)
Interrupt counts are INTA 5, INTB 6, EXPA 4 and EXPB 5
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

PWM mode at 50 percent dutyINTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0007 · GPT2_PWM_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:50:22

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10
TOUT on GPIO5 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5

Pass / fail criteria

TOUT duty cycle is 50 percent and the period follows CNTRB, checked on the logic-analyser capture (result_output_img)
Interrupt counts are INTA 5, INTB 6, EXPA 4 and EXPB 5
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

PWM mode at 50 percent dutyINTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0008 · GPT3_PWM_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:56:06

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

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Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Soft reset, then PWM mode (MODE 3) with all four interrupts enabled, CNTRA 499, CNTRB 999 (50 percent duty), prescaler /8 and DIV 10
TOUT on GPIO6 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for 6 INTB interrupts, then checks the counts INTA 5, INTB 6, EXPA 4 and EXPB 5

Pass / fail criteria

TOUT duty cycle is 50 percent and the period follows CNTRB, checked on the logic-analyser capture (result_output_img)
Interrupt counts are INTA 5, INTB 6, EXPA 4 and EXPB 5
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

PWM mode at 50 percent dutyINTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0009 · GPT0_SINGLE_PULSE_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:04:25

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22)
TOUT pulse on GPIO3 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for two INTA interrupts and then checks that exactly two occurred

Pass / fail criteria

TOUT pulse width matches CNTRA 100, checked on the logic-analyser capture (result_output_img)
Exactly two INTA interrupts (pulse start and pulse end)
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Single pulse mode

1 result

TC_GPT_0010 · GPT0_SINGLE_PULSE_MODE_CLEAR_SPS

PASS1/1

P2readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:04:02

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts)
The GPT is disabled and re-enabled for a second pulse
After the third INTA the code clears SPS part-way through the pulse

Pass / fail criteria

The second TOUT pulse is shorter than the first, checked on the logic-analyser capture (result_output_img)
INTA count reaches three
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Single pulse stopped early by clearing SPS

1 result

TC_GPT_0011 · GPT0_SINGLE_PULSE_MODE_CNTRA

PASS1/1

P2readyowner Chandanarun autosetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:04:12

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs
CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2)
TOUT on GPIO3 for observation

Pass / fail criteria

No HardFault and the SoC stays functional for CNTRA 3, 2, 1 and 0
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Single pulse mode with CNTRA 0 to 3

1 result

TC_GPT_0012 · GPT1_SINGLE_PULSE_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:26:02

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22)
TOUT pulse on GPIO4 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for two INTA interrupts and then checks that exactly two occurred

Pass / fail criteria

TOUT pulse width matches CNTRA 100, checked on the logic-analyser capture (result_output_img)
Exactly two INTA interrupts (pulse start and pulse end)
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Single pulse mode

1 result

TC_GPT_0013 · GPT1_SINGLE_PULSE_MODE_CLEAR_SPS

PASS1/1

P2readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:24:20

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts)
The GPT is disabled and re-enabled for a second pulse
After the third INTA the code clears SPS part-way through the pulse

Pass / fail criteria

The second TOUT pulse is shorter than the first, checked on the logic-analyser capture (result_output_img)
INTA count reaches three
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Single pulse stopped early by clearing SPS

1 result

TC_GPT_0014 · GPT1_SINGLE_PULSE_MODE_CNTRA

PASS1/1

P2readyowner Chandanarun autosetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:25:45

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs
CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2)
TOUT on GPIO4 for observation

Pass / fail criteria

No HardFault and the SoC stays functional for CNTRA 3, 2, 1 and 0
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Single pulse mode with CNTRA 0 to 3

1 result

TC_GPT_0015 · GPT2_SINGLE_PULSE_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:53:39

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22)
TOUT pulse on GPIO5 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for two INTA interrupts and then checks that exactly two occurred

Pass / fail criteria

TOUT pulse width matches CNTRA 100, checked on the logic-analyser capture (result_output_img)
Exactly two INTA interrupts (pulse start and pulse end)
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Single pulse mode

1 result

TC_GPT_0016 · GPT2_SINGLE_PULSE_MODE_CLEAR_SPS

PASS1/1

P2readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:51:26

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts)
The GPT is disabled and re-enabled for a second pulse
After the third INTA the code clears SPS part-way through the pulse

Pass / fail criteria

The second TOUT pulse is shorter than the first, checked on the logic-analyser capture (result_output_img)
INTA count reaches three
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Single pulse stopped early by clearing SPS

1 result

TC_GPT_0017 · GPT2_SINGLE_PULSE_MODE_CNTRA

PASS1/1

P2readyowner Chandanarun autosetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:52:50

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs
CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2)
TOUT on GPIO5 for observation

Pass / fail criteria

No HardFault and the SoC stays functional for CNTRA 3, 2, 1 and 0
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Single pulse mode with CNTRA 0 to 3

1 result

TC_GPT_0018 · GPT3_SINGLE_PULSE_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:56:53

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Soft reset, then single pulse mode (MODE 2) with SPS=1, CNTRA 100, prescaler /8 and DIV 10 (/22)
TOUT pulse on GPIO6 and an interrupt marker pulse on GPIO14 for each GPT interrupt
The code waits for two INTA interrupts and then checks that exactly two occurred

Pass / fail criteria

TOUT pulse width matches CNTRA 100, checked on the logic-analyser capture (result_output_img)
Exactly two INTA interrupts (pulse start and pulse end)
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Single pulse mode

1 result

TC_GPT_0019 · GPT3_SINGLE_PULSE_MODE_CLEAR_SPS

PASS1/1

P2readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:56:20

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Single pulse mode with CNTRA 100; the first pulse runs to completion (two INTA interrupts)
The GPT is disabled and re-enabled for a second pulse
After the third INTA the code clears SPS part-way through the pulse

Pass / fail criteria

The second TOUT pulse is shorter than the first, checked on the logic-analyser capture (result_output_img)
INTA count reaches three
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Single pulse stopped early by clearing SPS

1 result

TC_GPT_0020 · GPT3_SINGLE_PULSE_MODE_CNTRA

PASS1/1

P2readyowner Chandanarun autosetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:56:28

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Single pulse mode run four times with CNTRA 3, 2, 1 and 0, disabling the GPT between runs
CNTRA below 3 is outside the documented range (reference manual 14.8.1: CNTRA must be greater than 2)
TOUT on GPIO6 for observation

Pass / fail criteria

No HardFault and the SoC stays functional for CNTRA 3, 2, 1 and 0
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Single pulse mode with CNTRA 0 to 3

1 result

TC_GPT_0021 · GPT0_GPT1_Cascade_test

In development

owner unassignedexecution tbd

Last runNot run yet

BoardVAAK001 RevA

Bugsnone

Test description

GPT cascading test,Providing tout of gpt0 as clock to gpt1 as aux_clk & observing the gpt1 tout behaviour , considering the test as 32bit counter
GPIO4 PAD used as muxing to observe tout.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
GPIO_4 ==>J1(23) Logic Analyzer - Displays interrupt signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays gpt1 tout signal
logger GPIO5 ==> J1(25) ==> USB-to-UART(TX) ==> PC

Features and configuration

GPT0 GPT1 Cascade Test

1 result

TC_GPT_0021 · GPT0_GPT1_Cascade_test

In development

owner unassignedexecution tbd

Last runNot run yet

BoardVAAK001 RevA

Bugsnone

Test description

GPT cascading test,Providing tout of gpt0 as clock to gpt1 as aux_clk & observing the gpt1 tout behaviour , considering the test as 32bit counter
GPIO4 PAD used as muxing to observe tout.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
GPIO_4 ==>J1(23) Logic Analyzer - Displays interrupt signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays gpt1 tout signal
logger GPIO5 ==> J1(25) ==> USB-to-UART(TX) ==> PC

Features and configuration

GPT0 GPT1 Cascade Test

1 result

TC_GPT_0021 · GPT0_GPT1_Cascade_test

PASS1/1

owner unassignedexecution tbd

Last run02-Sep-2026 19:16:07

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

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Test description

GPT cascading test,Providing tout of gpt0 as clock to gpt1 as aux_clk & observing the gpt1 tout behaviour , considering the test as 32bit counter
GPIO4 PAD used as muxing to observe tout.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
GPIO_4 ==>J1(23) Logic Analyzer - Displays interrupt signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays gpt1 tout signal
logger GPIO5 ==> J1(25) ==> USB-to-UART(TX) ==> PC

Features and configuration

GPT0 GPT1 Cascade Test

1 result

TC_GPT_0022 · GPT0_STD_TIMER_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:04:49

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

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Test description

Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock
Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count)
TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the four values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Standard timer mode on FCLKINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0023 · GPT1_STD_TIMER_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:27:00

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

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Test description

Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock
Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count)
TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the four values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Standard timer mode on FCLKINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0024 · GPT2_STD_TIMER_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:54:21

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

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Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock
Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count)
TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the four values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Standard timer mode on FCLKINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0025 · GPT3_STD_TIMER_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:57:55

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Standard timer mode (MODE 0) on FCLK with prescaler /8 and DIV 14 (/30), about 61 kHz GPT clock
Four CNTRB values in turn: 62, 6200, 62000 and 65535 (about 1 ms, 100 ms, 1 s and the maximum count)
TOUT toggles at each rollover; each GPT interrupt pulses GPIO14 (VOL_CSENSE)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts, then disables the GPT

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the four values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Standard timer mode on FCLKINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0026 · GPT1_COMPARE_MATCH_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:15:49

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

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Test description

Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled
Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2
Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8)
Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB
TOUT on GPIO4 and an interrupt marker pulse on GPIO14 for each GPT interrupt

Pass / fail criteria

TOUT toggles at CNTRA and the period follows CNTRB for each pair, checked on the logic-analyser captures (result_output_img)
New CNTRA and CNTRB values take effect after rollover for pairs 6 and 7, checked on the captures
INTA, INTB, EXPA and EXPB all occur
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Compare match modeCompare ratios 25/50/75 percent and minimum and maximum countsCNTRA and CNTRB update while running (shadow load)INTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0027 · GPT2_COMPARE_MATCH_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:50:03

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled
Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2
Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8)
Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB
TOUT on GPIO5 and an interrupt marker pulse on GPIO14 for each GPT interrupt

Pass / fail criteria

TOUT toggles at CNTRA and the period follows CNTRB for each pair, checked on the logic-analyser captures (result_output_img)
New CNTRA and CNTRB values take effect after rollover for pairs 6 and 7, checked on the captures
INTA, INTB, EXPA and EXPB all occur
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Compare match modeCompare ratios 25/50/75 percent and minimum and maximum countsCNTRA and CNTRB update while running (shadow load)INTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0028 · GPT0_COMPARE_MATCH_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:03:35

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled
Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2
Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8)
Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB
TOUT on GPIO3 and an interrupt marker pulse on GPIO14 for each GPT interrupt

Pass / fail criteria

TOUT toggles at CNTRA and the period follows CNTRB for each pair, checked on the logic-analyser captures (result_output_img)
New CNTRA and CNTRB values take effect after rollover for pairs 6 and 7, checked on the captures
INTA, INTB, EXPA and EXPB all occur
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Compare match modeCompare ratios 25/50/75 percent and minimum and maximum countsCNTRA and CNTRB update while running (shadow load)INTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0029 · GPT3_COMPARE_MATCH_MODE

PASS1/1

P2readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:55:53

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Compare match mode (MODE 1) with INTA, INTB, EXPA and EXPB enabled
Eight CNTRA/CNTRB pairs in turn: 38/50, 100/400, 400/800, 750/1000, 60000/65535, 15000/20000, 22000/30000 and 1/2
Pairs 2 to 4 give 25, 50 and 75 percent ratios; pair 5 is the maximum count and pair 8 the minimum (prescaler /8)
Pairs 6 and 7 rewrite CNTRA 400 and CNTRB 800 while the timer runs, after the second INTB
TOUT on GPIO6 and an interrupt marker pulse on GPIO14 for each GPT interrupt

Pass / fail criteria

TOUT toggles at CNTRA and the period follows CNTRB for each pair, checked on the logic-analyser captures (result_output_img)
New CNTRA and CNTRB values take effect after rollover for pairs 6 and 7, checked on the captures
INTA, INTB, EXPA and EXPB all occur
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Compare match modeCompare ratios 25/50/75 percent and minimum and maximum countsCNTRA and CNTRB update while running (shadow load)INTA, INTB, EXPA and EXPB interrupts

1 result

TC_GPT_0030 · GPT0_STD_TIMER_MODE_LFOSC

PASS1/1

P1readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:04:35

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

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Test description

Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input
Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock
Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the three values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Standard timer mode on AUXCLK from the LF oscillatorINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0031 · GPT1_STD_TIMER_MODE_LFOSC

PASS1/1

P1readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:26:45

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input
Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock
Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the three values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

Standard timer mode on AUXCLK from the LF oscillatorINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0032 · GPT2_STD_TIMER_MODE_LFOSC

PASS1/1

P1readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:54:00

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input
Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock
Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the three values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Standard timer mode on AUXCLK from the LF oscillatorINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0033 · GPT3_STD_TIMER_MODE_LFOSC

PASS1/1

P1readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run31-Aug-2026 13:57:23

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

Trigger router sends the LF oscillator clock (about 126 kHz) to the GPT AUXCLK input
Standard timer mode with CLKSEL=1 (AUXCLK), prescaler /1 and DIV 4 (/10), about 12.6 kHz GPT clock
Three CNTRB values in turn: 63000, 13 and 1000 (about 5 s, 1 ms and 80 ms)
For each value the code waits for INTB, EXPB and at least 7 INTB interrupts

Pass / fail criteria

TOUT period on the logic analyser matches CNTRB for each of the three values (captures in result_output_img)
INTB and EXPB occur for each value, with at least 7 INTB interrupts
Final TEST_RESULT is [[PASS]] and the run reaches [[TEST_END]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

Standard timer mode on AUXCLK from the LF oscillatorINTB and EXPB interrupts in standard timer mode

1 result

TC_GPT_0034 · GPT3_LPM_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT3_TOUT_LA · time tbdexecution tbd

Last run21-Sep-2026 12:22:28

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.
Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80
After the first INTB the CPU enters idle and waits for interrupt
After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt
After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt
The test ends after 8 INTB interrupts

Pass / fail criteria

The CPU wakes from idle, sleep and deep sleep on the GPT interrupt and the run reaches [[TEST_END]]
TOUT duty cycle changes after CNTRA is updated, checked on the logic-analyser capture
Final TEST_RESULT is [[PASS]]

Hardware connection

GPT3 TOUT on GPIO6 ==> J1(27) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

GPT interrupt wakes the CPU from idle, sleep and deep sleepCNTRA update while the CPU is in low-power mode

1 result

TC_GPT_0035 · GPT0_LPM_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT0_TOUT_LA · time tbdexecution tbd

Last run21-Sep-2026 12:20:29

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.

Test description

GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80
After the first INTB the CPU enters idle and waits for interrupt
After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt
After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt
The test ends after 8 INTB interrupts

Pass / fail criteria

The CPU wakes from idle, sleep and deep sleep on the GPT interrupt and the run reaches [[TEST_END]]
TOUT duty cycle changes after CNTRA is updated, checked on the logic-analyser capture
Final TEST_RESULT is [[PASS]]

Hardware connection

GPT0 TOUT on GPIO3 ==> J1(20) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

GPT interrupt wakes the CPU from idle, sleep and deep sleepCNTRA update while the CPU is in low-power mode

1 result

TC_GPT_0036 · GPT1_LPM_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT1_TOUT_LA · time tbdexecution tbd

Last run21-Sep-2026 12:21:50

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.

Test description

GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80
After the first INTB the CPU enters idle and waits for interrupt
After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt
After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt
The test ends after 8 INTB interrupts

Pass / fail criteria

The CPU wakes from idle, sleep and deep sleep on the GPT interrupt and the run reaches [[TEST_END]]
TOUT duty cycle changes after CNTRA is updated, checked on the logic-analyser capture
Final TEST_RESULT is [[PASS]]

Hardware connection

GPT1 TOUT on GPIO4 ==> J1(23) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART1 TX on GPIO5 ==> J1(25) ==> USB-to-UART ==> PC

Features and configuration

GPT interrupt wakes the CPU from idle, sleep and deep sleepCNTRA update while the CPU is in low-power mode

1 result

TC_GPT_0037 · GPT2_LPM_MODE

PASS1/1

P1readyowner Chandanarun manualsetup GPT2_TOUT_LA · time tbdexecution tbd

Last run21-Sep-2026 12:22:06

Silicon1.0

BoardVK001_ATE_Rev00

Firmware commitunknown

Bugsnone

Filesreport · log

Open issues

Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.
Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.

Test description

GPT in PWM mode with all four interrupts enabled, CNTRA 400, CNTRB 900, DIV 0x80
After the first INTB the CPU enters idle and waits for interrupt
After the third INTB the CPU enters sleep, CNTRA is changed to 660 and the CPU waits for interrupt
After the first EXPB and second INTA the CPU enters deep sleep and waits for interrupt
The test ends after 8 INTB interrupts

Pass / fail criteria

The CPU wakes from idle, sleep and deep sleep on the GPT interrupt and the run reaches [[TEST_END]]
TOUT duty cycle changes after CNTRA is updated, checked on the logic-analyser capture
Final TEST_RESULT is [[PASS]]

Hardware connection

GPT2 TOUT on GPIO5 ==> J1(25) ==> logic analyser
GPT interrupt marker on GPIO14 (VOL_CSENSE) ==> J1(13) ==> logic analyser, one pulse per GPT interrupt
Logger UART0 TX ==> J1(21) ==> USB-to-UART ==> PC (TX pad to be confirmed)

Features and configuration

GPT interrupt wakes the CPU from idle, sleep and deep sleepCNTRA update while the CPU is in low-power mode

1 result

TC_GPT_0038 · GPT_CLOCK_SELECT

Not implemented

P2plannedowner Chandanarun autono wiringexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Switch CLKSEL from FCLK to AUXCLK and back while the GPT runs; the switch takes effect after two clock cycles
Repeat the switch with GFB=1 (glitch-free mux bypassed)
Run with prescaler /1 and /8, and with DIV 0 (/2) and DIV 255 (/512)
Measure the INTB period with SysTick for each case and compare it with the value computed from the clock settings

Pass / fail criteria

Measured period matches the computed period within the agreed tolerance for every case
No missing or extra interrupt around a clock switch
Expected results = 4 x 7 = 28

Hardware connection

Defined when implemented

Features and configuration

Clock source switch between FCLK and AUXCLK while runningGlitch-free mux bypass (GFB)Prescaler and divider range

instance 4 × case 7 = 28 results

TC_GPT_0039 · GPT_OUTPUT_CONTROL

Not implemented

P2plannedowner Chandanarun manualsetup GPT_TOUT_ALL_LA · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Run PWM mode with INV=0 and then INV=1 and compare the TOUT waveforms
Run with TOEN=0 and check that the pad stays idle while the counter runs (COUNT keeps changing)
Set PS while running, check that COUNT holds, then clear PS and check that counting resumes

Pass / fail criteria

TOUT is inverted with INV=1, checked on the logic analyser
No TOUT activity on the pad with TOEN=0 while COUNT changes
COUNT holds while PS=1 and resumes after PS is cleared
Expected results = 4 x 3 = 12

Hardware connection

Defined when implemented

Features and configuration

Output polarity invert (INV)Output enable (TOEN)Pause and resume (PS)

instance 4 × case 3 = 12 results

TC_GPT_0040 · GPT_COUNT_AND_STATUS

Not implemented

P2plannedowner Chandanarun autono wiringexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Read COUNT while the GPT runs, repeating each read until two reads match (reference manual 14.8.1)
Check that COUNT increases between reads and wraps at CNTRB
Check that BUSY is set when GPTEN is set, and that a re-enable after disable takes effect only after BUSY clears
Check SYNBUSY around a register write

Pass / fail criteria

COUNT values increase and wrap at CNTRB
BUSY and SYNBUSY follow the behaviour in the reference manual
Expected results = 4 x 4 = 16

Hardware connection

Defined when implemented

Features and configuration

COUNT register read while runningBUSY and SYNBUSY status

instance 4 × case 4 = 16 results

TC_GPT_0041 · GPT_TRIGGER_IN_OUT

Not implemented

P2plannedowner Chandanarun autono wiringexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Route a trigger source to gpt_trg_in through the trigger router and check that GPTEN is set by the pulse
Route gpt_trg_out to another block through the trigger router and count one pulse per TOUT toggle
Repeat the trigger-out check with the CPU in sleep, without waking the CPU

Pass / fail criteria

GPTEN is set by the trigger-in pulse and the GPT starts counting
The receiving block counts one trigger per TOUT toggle, also while the CPU sleeps
Expected results = 4 x 3 = 12

Hardware connection

Defined when implemented

Features and configuration

Trigger input starts the timer (gpt_trg_in)Trigger output at each TOUT toggle (gpt_trg_out)Trigger output while the CPU is in low-power mode

instance 4 × case 3 = 12 results

TC_GPT_0042 · GPT_INTERRUPT_ENABLES

Not implemented

P2plannedowner Chandanarun autono wiringexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Enable INTAEN, INTBEN, EXPAEN and EXPBEN one at a time and check that only the enabled source raises the IRQ
Check that the status bits still set when their enable bit is clear
Write 1 to one status bit and check that only that bit clears
Raise several sources together and check that they arrive on the single GPT IRQ line
Run with CNTRA and CNTRB below 5 and check that TOUT runs but no interrupt is raised (reference manual 14.8.1)

Pass / fail criteria

Each enable bit gates only its own source
Writing 1 clears only the written status bit
CNTRA and CNTRB below 5 give TOUT activity with no interrupt, or the behaviour is recorded for the reference manual
Expected results = 4 x 7 = 28

Hardware connection

Defined when implemented

Features and configuration

Interrupt enable bits gate each sourceStatus bits clear only on write 1Interrupt sources share one IRQ lineNo interrupt for CNTRA and CNTRB below 5

instance 4 × case 7 = 28 results