VK001 Post-Si ValidationHW101x · silicon 1.0
Dashboard / SYSTICK

SYSTICK

1 test case · SYSTICK · silicon 1.0 · generated 02-Nov-2026 14:11:07

PASS 1
No priority set1 of 1 passed · 0 not passed
Bench time (estimates)
TestsExecution (min – max)Setup (min – max)Total (min – max)Estimated
All tests1tbd-tbd0 of 1 tests
Not passed0---0 of 0 tests
Feature coverage · 1 features · 1 verified · 0 failing · 0 open
FeatureCovered byFeature status
Delay Generation
0001
PASS

Test cases

1 of 1 shown
Priority
Status
Test caseName and test descriptionPriorityOwnerStatusLast runRun mode · setup · execution
TC_SYSTICK_0001
SYSTICK_DELAY
  • Initialize SysTick timer.
  • Generate delay using SysTick.
  • Toggle GPIO5 periodically.
  • Verify correct delay timing.
  • Check output waveform.
  • Report PASS/FAIL.
-unassignedPASS
1/1
23-Sep-2026 15:49:00
-
-
execution tbd

TC_SYSTICK_0001 · SYSTICK_DELAY

PASS1/1
owner unassignedexecution tbd
Last run23-Sep-2026 15:49:00
Silicon1.0
BoardVAAK001 RevA
Firmware commitunknown
Bugsnone
Filesreport · log

Test description

  • Initialize SysTick timer.
  • Generate delay using SysTick.
  • Toggle GPIO5 periodically.
  • Verify correct delay timing.
  • Check output waveform.
  • Report PASS/FAIL.

Pass / fail criteria

-

Hardware connection

  • The connections are made on the ATE board.
  • GPIO5 => Logic Analyzer / Oscilloscope
  • logger GPIO3 => J1(21) => USB-to-UART(TX) => PC

Features and configuration

Delay Generation

1 result

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