UART

16 test cases · UART0, UART1 · silicon 1.0 · generated 02-Nov-2026 14:11:07

PASS 7In development 3Not implemented 6

P1 · customer sample gate7 of 11 passed · 4 not passed

P2 · full validation0 of 5 passed · 5 not passed

Bench time (estimates)

	Tests	Execution (min – max)	Setup (min – max)	Total (min – max)	Estimated
All tests	16	tbd	tbd	tbd	1 of 16 tests 0 of 7 setups
Not passed	9	tbd	tbd	tbd	0 of 9 tests 0 of 5 setups

Feature coverage · 33 features · 14 verified · 0 failing · 19 open

Feature	Covered by	Feature status
Register reset values and R/W access	0001 0002	PASS
Soft reset restores defaults	0001 0002	PASS
Bidirectional transfer UART0 <-> UART1	0003 0004 0005	PASS
Word length 5-8 bits	0003 0004 0005	PASS
Parity none/even/odd	0003 0004 0005 0006	PASS
Stop bits 1/2	0003 0004 0005 0006	PASS
UART0 TX/RX on pins 7/6	0003 0005	PASS
UART1 TX/RX on pins 10/11	0003 0004	PASS
RX data interrupt	0003 0004 0005	PASS
UART0 TX/RX on pins 8/9	0004	PASS
UART1 TX/RX on pins 23/15	0005	PASS
Full-duplex with external device	0006	PASS
Baud rates 300-460800 except 384000 vs external reference	0006	PASS
Overrun interrupt	0007	PASS
TX interrupt	0008	In development
Baud error on INTOSC vs EXT CLK	0009	Not implemented
Fractional baud divisor	0009	Not implemented
Parity error detection	0010	Not implemented
Framing error detection	0010	Not implemented
Break detection	0010	Not implemented
Receiver timeout interrupt	0010	Not implemented
Start-of-frame interrupt	0010	Not implemented
FIFO flush RX/TX	0012	Not implemented
FIFO count RX/TX	0012	Not implemented
FIFO watermark RX/TX	0012	Not implemented
Single-wire half-duplex with internal pull-up	0015	In development
Wake from deep sleep on UART RX	0017	In development
Throughput under bus-matrix load	0018	Not implemented
1-hour PRBS loopback stress	0018	Not implemented
MSb-first data order	0020	Not implemented
Data polarity inversion	0020	Not implemented
Glitch-free clock mux bypass	0020	Not implemented
Hardware flow control RTS/CTS	0021	Not implemented

Test cases

16 of 16 shown

Priority

Status

Test case	Name and test description	Priority	Owner	Status	Last run	Run mode · setup · execution
TC_UART_0001	UART0_REG_RW Check reset values of UART0 CTRL, STS, BCTRL, FCS, TXD and RXD Walking 1s, 0s, 5s and As pattern test on CTRL, STS, BCTRL and FCS Soft reset through CTRL, then re-check all reset values Random-data write/read on CTRL, STS, BCTRL and FCS Byte, half-word and word accesses (hsize/pstrb check) Invalid accesses (RXD write, RXD read, random unmapped addresses in the UART block) in reset scenarios C_RESET2-C_RESET7; each is expected to raise a HardFault and system reset, after which the test continues	P1	Jyeshta	PASS 1/1	01-Sep-2026 00:09:21	auto no wiring 1 min – 2 min
TC_UART_0002	UART1_REG_RW Check reset values of UART1 CTRL, STS, BCTRL, FCS, TXD and RXD Walking 1s, 0s, 5s and As pattern test on CTRL, STS, BCTRL and FCS Soft reset through CTRL, then re-check all reset values Random-data write/read on CTRL, STS, BCTRL and FCS Byte, half-word and word accesses (hsize/pstrb check) Invalid accesses (RXD write, RXD read, random unmapped addresses in the UART block) in reset scenarios C_RESET2-C_RESET7; each is expected to raise a HardFault and system reset, after which the test continues	P1	Jyeshta	PASS 1/1	01-Sep-2026 00:09:31	auto no wiring execution tbd
TC_UART_0003	UART_EXT_LOOPBACK_IOSET0 UART0 TX is connected to UART1 RX and UART1 TX to UART0 RX UART0 sends a 64-word pattern seeded 0x55, UART1 sends one seeded 0xAA RX on both UARTs is interrupt based (RX data and RX timeout interrupts) Full sweep of baud rate, data width, parity and stop bits Result per configuration is logged on the soft UART	P1	Jyeshta	PASS 390/390	01-Sep-2026 00:08:45	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0004	UART_EXT_LOOPBACK_IOSET1 UART0 TX is connected to UART1 RX and UART1 TX to UART0 RX UART0 sends a 64-word pattern seeded 0x55, UART1 sends one seeded 0xAA RX on both UARTs is interrupt based (RX data and RX timeout interrupts) Full sweep of baud rate, data width, parity and stop bits Result per configuration is logged on the soft UART	P1	Jyeshta	PASS 390/390	01-Sep-2026 00:08:55	auto UART_LOOP_IOSET1 execution tbd
TC_UART_0005	UART_EXT_LOOPBACK_IOSET2 UART0 TX is connected to UART1 RX and UART1 TX to UART0 RX UART1 uses its alternate pins, TX on GPIO_0 (SWDIO pin) and RX on GPIO_7 Test waits for GPIO_4 to stay high for 500 ms before starting, so the debugger can be detached Pin mux is restored to default at the end of the test UART0 sends a 64-word pattern seeded 0x55, UART1 sends one seeded 0xAA RX on both UARTs is interrupt based (RX data and RX timeout interrupts) Full sweep of baud rate, data width, parity and stop bits Result per configuration is logged on the soft UART	P1	Jyeshta	PASS 390/390	07-Sep-2026 19:28:27	manual UART_LOOP_IOSET2 execution tbd
TC_UART_0006	UART_EXT_DUAL_FDX UART0 and UART1 are each connected to a PC USB-UART adapter; uart_pc.py runs on the PC UART0 sends a 64-byte sequence seeded 0x55, UART1 one seeded 0xAA uart_pc.py answers each port with the inverse payload as soon as the first byte arrives, forcing simultaneous TX and RX PC checks the SoC data and replies with a 65th byte, & for pass or ! for fail RX on both UARTs is interrupt based; results are logged on the soft UART	P1	Jyeshta	PASS 432/432	01-Sep-2026 00:09:11	host UART_PC_DUAL execution tbd
TC_UART_0007	UART_OVERRUN_INTERRUPT UART0 and UART1 send 9 words to each other over the loopback wiring RX data interrupt is disabled and the RX FIFO is not read, so the FIFO overruns Overrun interrupt is enabled; the ISR records the overrun for each UART	P1	Chandana	PASS 1/1	01-Sep-2026 00:08:37	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0008	UART_TX_INTERRUPT UART0 and UART1 each transmit 64 words, refilling the TX FIFO only from the TX interrupt Receiving side uses the RX data interrupt as in TC_UART_0003	P1	Jyeshta	In development	-	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0009	UART_BAUD_ACCURACY Transmit a continuous 0x55 pattern on the TX pin of each UART at each baud rate in the list Rates cover whole-number divisors (9600, 115200, 460800) and a fractional divisor (384000 needs 2.4 on 14.7456 MHz) Measure the bit time on the TX line with a scope or logic analyser Run on the internal oscillator and with an external 14.7456 MHz clock on EXT_CLK	P1	unassigned	Not implemented	-	manual UART_BAUD_MEAS execution tbd
TC_UART_0010	UART_RX_STATUS_INTERRUPTS PARITY_ERROR - transmitter sends even parity into a receiver set for odd parity, then odd into even FRAMING_ERROR - transmitter sends back-to-back frames with 1 stop bit into a receiver set for 2 stop bits BREAK - transmitter sends a break condition RX_TIMEOUT - transmitter sends fewer words than the RX watermark and stops; the timeout is timed with SysTick START_OF_FRAME - transmitter sends single frames with idle gaps between them Each condition is run UART0 -> UART1 and then UART1 -> UART0	P2	unassigned	Not implemented	-	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0012	UART_FIFO Each check below is run on UART0 and then on UART1 Fill the TX FIFO with the transmitter disabled and check the TX count at each level Receive known numbers of words and check the RX count Flush each FIFO and check its count returns to zero Step the RX and TX watermarks through their range and check the watermark interrupts	P2	unassigned	Not implemented	-	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0015	UART_HALF_DUPLEX Single-wire half-duplex exchange with the TWS earbud at the baud rate the customer will use Repeated for each UART's single-wire pin and each internal pull-up setting For each run, increase the baud rate until communication fails to find the highest working rate Capture the waveform and record rise and fall times for each run	P1	Jyeshta	In development	-	manual UART_HDX_EARBUD execution tbd
TC_UART_0017	UART_DEEPSLEEP_WAKEUP Enable UART RX as a deep-sleep wake source and enter deep sleep PC sends a frame to the sleeping SoC SoC wakes, receives the frame and logs the result Done once with the wake frame on UART0 and once on UART1	P1	Jyeshta	In development	-	host UART_PC_DUAL execution tbd
TC_UART_0018	UART_LOAD_STRESS THROUGHPUT - time the TC_UART_0003 transfer with TX/RX interrupts while the CPU reads and writes 1 KB of SRAM in a loop (X), then with the CPU idle in while(1) (Y); raise the baud rate until data is corrupted SOAK - UART0 <-> UART1 loopback with pseudo-random data for 1 hour while the CPU keeps the SRAM traffic running	P2	unassigned	Not implemented	-	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0020	UART_MODE_OPTIONS MSB_FIRST - UART0 transmits MSb-first while UART1 receives LSb-first, then both ends MSb-first POLARITY_INVERTED - invert polarity on one end only, then on both ends CLK_MUX_BYPASS - run the loopback with the glitch-free mux in use and with the bypass enabled, changing the setting while idle between transfers Each mode is run UART0 -> UART1 and then UART1 -> UART0	P2	unassigned	Not implemented	-	auto UART_LOOP_IOSET0 execution tbd
TC_UART_0021	UART_HW_FLOW_CONTROL Connect UART0 RTS/CTS to UART1 CTS/RTS Hold off the receiver and check the transmitter stops while CTS is deasserted Run UART0 -> UART1 and then UART1 -> UART0	P2	unassigned	Not implemented	-	auto UART_FLOW_CTRL execution tbd

TC_UART_0001 · UART0_REG_RW

PASS1/1

P1readyowner Jyeshtarun autono wiringexecution 1 min – 2 min

Last run01-Sep-2026 00:09:21

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Check reset values of UART0 CTRL, STS, BCTRL, FCS, TXD and RXD
Walking 1s, 0s, 5s and As pattern test on CTRL, STS, BCTRL and FCS
Soft reset through CTRL, then re-check all reset values
Random-data write/read on CTRL, STS, BCTRL and FCS
Byte, half-word and word accesses (hsize/pstrb check)
Invalid accesses (RXD write, RXD read, random unmapped addresses in the UART block) in reset scenarios C_RESET2-C_RESET7; each is expected to raise a HardFault and system reset, after which the test continues

Pass / fail criteria

All register reads match the expected values after masking (reset, pattern, random, all access sizes)
Each invalid access raises the expected HardFault and the test resumes after reset
Final TEST_RESULT is [[PASS]] with no [[FAIL]] events

Hardware connection

No external connections apart from the soft UART logger

Features and configuration

1 result

TC_UART_0002 · UART1_REG_RW

PASS1/1

P1readyowner Jyeshtarun autono wiringexecution tbd

Last run01-Sep-2026 00:09:31

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Check reset values of UART1 CTRL, STS, BCTRL, FCS, TXD and RXD
Walking 1s, 0s, 5s and As pattern test on CTRL, STS, BCTRL and FCS
Soft reset through CTRL, then re-check all reset values
Random-data write/read on CTRL, STS, BCTRL and FCS
Byte, half-word and word accesses (hsize/pstrb check)
Invalid accesses (RXD write, RXD read, random unmapped addresses in the UART block) in reset scenarios C_RESET2-C_RESET7; each is expected to raise a HardFault and system reset, after which the test continues

Pass / fail criteria

All register reads match the expected values after masking (reset, pattern, random, all access sizes)
Each invalid access raises the expected HardFault and the test resumes after reset
Final TEST_RESULT is [[PASS]] with no [[FAIL]] events

Hardware connection

No external connections apart from the soft UART logger

Features and configuration

1 result

TC_UART_0003 · UART_EXT_LOOPBACK_IOSET0

PASS390/390

P1readyowner Jyeshtarun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last run01-Sep-2026 00:08:45

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

UART0 TX is connected to UART1 RX and UART1 TX to UART0 RX
UART0 sends a 64-word pattern seeded 0x55, UART1 sends one seeded 0xAA
RX on both UARTs is interrupt based (RX data and RX timeout interrupts)
Full sweep of baud rate, data width, parity and stop bits
Result per configuration is logged on the soft UART

Pass / fail criteria

UART1 RX buffer matches UART0 TX buffer for all 64 words
UART0 RX buffer matches UART1 TX buffer for all 64 words
Expected results = 13 x 5 x 3 x 2 = 390; fewer results means the run did not finish

Hardware connection

GPIO_1 UART_0_TX ==> 12 (J11) ==> GPIO_6 UART_1_RX ==> 32 (J11)
GPIO_2 UART_0_RX ==> 16 (J11) ==> GPIO_5 UART_1_TX ==> 28 (J11)
SOFT UART Logger ==> GPIO_3 20 (J11)
Common GND connection required

Features and configuration

Bidirectional transfer UART0 <-> UART1Word length 5-8 bitsParity none/even/oddStop bits 1/2UART0 TX/RX on pins 7/6UART1 TX/RX on pins 10/11RX data interrupt

baud_rates 13 × data_bits 5 × parity 3 × stop_bits 2 = 390 results

Results by configuration

Each cell: passed / run over PARITY, STOP

BAUD \ DATA	5	6	7	8	9
300	6/6	6/6	6/6	6/6	6/6
600	6/6	6/6	6/6	6/6	6/6
1200	6/6	6/6	6/6	6/6	6/6
2400	6/6	6/6	6/6	6/6	6/6
4800	6/6	6/6	6/6	6/6	6/6
9600	6/6	6/6	6/6	6/6	6/6
19200	6/6	6/6	6/6	6/6	6/6
38400	6/6	6/6	6/6	6/6	6/6
57600	6/6	6/6	6/6	6/6	6/6
115200	6/6	6/6	6/6	6/6	6/6
230400	6/6	6/6	6/6	6/6	6/6
384000	6/6	6/6	6/6	6/6	6/6
460800	6/6	6/6	6/6	6/6	6/6

BAUD \ DATA

300

6/6

600

6/6

1200

6/6

2400

6/6

4800

6/6

9600

6/6

19200

6/6

38400

6/6

57600

6/6

115200

6/6

230400

6/6

384000

6/6

460800

6/6

TC_UART_0004 · UART_EXT_LOOPBACK_IOSET1

PASS390/390

P1readyowner Jyeshtarun autosetup UART_LOOP_IOSET1 · time tbdexecution tbd

Last run01-Sep-2026 00:08:55

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

UART0 TX is connected to UART1 RX and UART1 TX to UART0 RX
UART0 sends a 64-word pattern seeded 0x55, UART1 sends one seeded 0xAA
RX on both UARTs is interrupt based (RX data and RX timeout interrupts)
Full sweep of baud rate, data width, parity and stop bits
Result per configuration is logged on the soft UART

Pass / fail criteria

UART1 RX buffer matches UART0 TX buffer for all 64 words
UART0 RX buffer matches UART1 TX buffer for all 64 words
Expected results = 13 x 5 x 3 x 2 = 390; fewer results means the run did not finish

Hardware connection

GPIO_3 UART_0_TX ==> 20 (J11) ==> GPIO_6 UART_1_RX ==> 32 (J11)
GPIO_4 UART_0_RX ==> 24 (J11) ==> GPIO_5 UART_1_TX ==> 28 (J11)
SOFT UART Logger ==> GPIO_13 30 (J13)
Common GND connection required

Features and configuration

Bidirectional transfer UART0 <-> UART1Word length 5-8 bitsParity none/even/oddStop bits 1/2UART0 TX/RX on pins 8/9UART1 TX/RX on pins 10/11RX data interrupt

baud_rates 13 × data_bits 5 × parity 3 × stop_bits 2 = 390 results

Results by configuration

Each cell: passed / run over PARITY, STOP

BAUD \ DATA	5	6	7	8	9
300	6/6	6/6	6/6	6/6	6/6
600	6/6	6/6	6/6	6/6	6/6
1200	6/6	6/6	6/6	6/6	6/6
2400	6/6	6/6	6/6	6/6	6/6
4800	6/6	6/6	6/6	6/6	6/6
9600	6/6	6/6	6/6	6/6	6/6
19200	6/6	6/6	6/6	6/6	6/6
38400	6/6	6/6	6/6	6/6	6/6
57600	6/6	6/6	6/6	6/6	6/6
115200	6/6	6/6	6/6	6/6	6/6
230400	6/6	6/6	6/6	6/6	6/6
384000	6/6	6/6	6/6	6/6	6/6
460800	6/6	6/6	6/6	6/6	6/6

BAUD \ DATA

300

6/6

600

6/6

1200

6/6

2400

6/6

4800

6/6

9600

6/6

19200

6/6

38400

6/6

57600

6/6

115200

6/6

230400

6/6

384000

6/6

460800

6/6

TC_UART_0005 · UART_EXT_LOOPBACK_IOSET2

PASS390/390

P1readyowner Jyeshtarun manualsetup UART_LOOP_IOSET2 · time tbdexecution tbd

Last run07-Sep-2026 19:28:27

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

UART0 TX is connected to UART1 RX and UART1 TX to UART0 RX
UART1 uses its alternate pins, TX on GPIO_0 (SWDIO pin) and RX on GPIO_7
Test waits for GPIO_4 to stay high for 500 ms before starting, so the debugger can be detached
Pin mux is restored to default at the end of the test
UART0 sends a 64-word pattern seeded 0x55, UART1 sends one seeded 0xAA
RX on both UARTs is interrupt based (RX data and RX timeout interrupts)
Full sweep of baud rate, data width, parity and stop bits
Result per configuration is logged on the soft UART

Pass / fail criteria

UART1 RX buffer matches UART0 TX buffer for all 64 words
UART0 RX buffer matches UART1 TX buffer for all 64 words
Expected results = 13 x 5 x 3 x 2 = 390; fewer results means the run did not finish

Hardware connection

GPIO_1 UART_0_TX ==> 12 (J11) ==> GPIO_7 UART_1_RX ==> 31 (J11)
GPIO_2 UART_0_RX ==> 16 (J11) ==> GPIO_0 UART_1_TX ==> 08 (J11)
SOFT UART Logger ==> GPIO_3 20 (J11)
GPIO_4 driven high for at least 500 ms to start the test
Common GND connection required

Features and configuration

Bidirectional transfer UART0 <-> UART1Word length 5-8 bitsParity none/even/oddStop bits 1/2UART0 TX/RX on pins 7/6UART1 TX/RX on pins 23/15RX data interrupt

baud_rates 13 × data_bits 5 × parity 3 × stop_bits 2 = 390 results

Results by configuration

Each cell: passed / run over PARITY, STOP

BAUD \ DATA	5	6	7	8	9
300	6/6	6/6	6/6	6/6	6/6
600	6/6	6/6	6/6	6/6	6/6
1200	6/6	6/6	6/6	6/6	6/6
2400	6/6	6/6	6/6	6/6	6/6
4800	6/6	6/6	6/6	6/6	6/6
9600	6/6	6/6	6/6	6/6	6/6
19200	6/6	6/6	6/6	6/6	6/6
38400	6/6	6/6	6/6	6/6	6/6
57600	6/6	6/6	6/6	6/6	6/6
115200	6/6	6/6	6/6	6/6	6/6
230400	6/6	6/6	6/6	6/6	6/6
384000	6/6	6/6	6/6	6/6	6/6
460800	6/6	6/6	6/6	6/6	6/6

BAUD \ DATA

300

6/6

600

6/6

1200

6/6

2400

6/6

4800

6/6

9600

6/6

19200

6/6

38400

6/6

57600

6/6

115200

6/6

230400

6/6

384000

6/6

460800

6/6

TC_UART_0006 · UART_EXT_DUAL_FDX

PASS432/432

P1readyowner Jyeshtarun hostsetup UART_PC_DUAL · time tbdexecution tbd

Last run01-Sep-2026 00:09:11

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

UART0 and UART1 are each connected to a PC USB-UART adapter; uart_pc.py runs on the PC
UART0 sends a 64-byte sequence seeded 0x55, UART1 one seeded 0xAA
uart_pc.py answers each port with the inverse payload as soon as the first byte arrives, forcing simultaneous TX and RX
PC checks the SoC data and replies with a 65th byte, & for pass or ! for fail
RX on both UARTs is interrupt based; results are logged on the soft UART

Pass / fail criteria

PC receives the exact 64-byte sequence from both SoC UARTs (SOURCE=PC result)
Both SoC UARTs receive the PC's 64-byte sequence correctly (SOURCE=UART result)
Expected results = 12 x 3 x 3 x 2 x 2 = 432; fewer results means the run did not finish

Hardware connection

GPIO_1 UART_0_TX ==> 12 (J11) ==> PC USB-UART adapter A RX
GPIO_2 UART_0_RX <== 16 (J11) <== PC USB-UART adapter A TX
GPIO_5 UART_1_TX ==> 28 (J11) ==> PC USB-UART adapter B RX
GPIO_6 UART_1_RX <== 32 (J11) <== PC USB-UART adapter B TX
SOFT UART Logger ==> GPIO_3 20 (J11)
Common GND between SoC board and both adapters

Features and configuration

Full-duplex with external deviceBaud rates 300-460800 except 384000 vs external referenceParity none/even/oddStop bits 1/2

baud_rates 12 × data_bits 3 × parity 3 × stop_bits 2 × source 2 = 432 results

Results by configuration

Each cell: passed / run over SOURCE, PARITY, STOP

BAUD \ DATA	6	7	8
300	12/12	12/12	12/12
600	12/12	12/12	12/12
1200	12/12	12/12	12/12
2400	12/12	12/12	12/12
4800	12/12	12/12	12/12
9600	12/12	12/12	12/12
19200	12/12	12/12	12/12
38400	12/12	12/12	12/12
57600	12/12	12/12	12/12
115200	12/12	12/12	12/12
230400	12/12	12/12	12/12
460800	12/12	12/12	12/12

BAUD \ DATA

300

12/12

600

12/12

1200

12/12

2400

12/12

4800

12/12

9600

12/12

19200

12/12

38400

12/12

57600

12/12

115200

12/12

230400

12/12

460800

12/12

TC_UART_0007 · UART_OVERRUN_INTERRUPT

PASS1/1

P1readyowner Chandanarun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last run01-Sep-2026 00:08:37

Silicon1.0

BoardVK001_RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

UART0 and UART1 send 9 words to each other over the loopback wiring
RX data interrupt is disabled and the RX FIFO is not read, so the FIFO overruns
Overrun interrupt is enabled; the ISR records the overrun for each UART

Pass / fail criteria

Overrun interrupt seen on both UART0 and UART1

Hardware connection

GPIO_1 UART_0_TX ==> 12 (J11) ==> GPIO_6 UART_1_RX ==> 32 (J11)
GPIO_2 UART_0_RX ==> 16 (J11) ==> GPIO_5 UART_1_TX ==> 28 (J11)
SOFT UART Logger ==> GPIO_3 20 (J11)
Common GND connection required

Features and configuration

Overrun interrupt

baud_rates 1 × data_bits 1 × parity 1 × stop_bits 1 = 1 results

TC_UART_0008 · UART_TX_INTERRUPT

In development

P1in_developmentowner Jyeshtarun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last runCode in development, not run

Board-

Bugsnone

Test description

UART0 and UART1 each transmit 64 words, refilling the TX FIFO only from the TX interrupt
Receiving side uses the RX data interrupt as in TC_UART_0003

Pass / fail criteria

All 64 words received correctly in both directions
TX interrupt count matches the number of FIFO refills expected

Hardware connection

Defined when implemented

Features and configuration

TX interrupt

1 result

TC_UART_0009 · UART_BAUD_ACCURACY

Not implemented

P1plannedowner unassignedrun manualsetup UART_BAUD_MEAS · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Transmit a continuous 0x55 pattern on the TX pin of each UART at each baud rate in the list
Rates cover whole-number divisors (9600, 115200, 460800) and a fractional divisor (384000 needs 2.4 on 14.7456 MHz)
Measure the bit time on the TX line with a scope or logic analyser
Run on the internal oscillator and with an external 14.7456 MHz clock on EXT_CLK

Pass / fail criteria

Measured bit time matches the rate computed from BAUDDIV and BAUDFRAC within the agreed error limit
Holds for both UARTs, every baud rate and both clock sources
Expected results = 2 x 2 x 4 = 16

Hardware connection

Defined when implemented

Features and configuration

Baud error on INTOSC vs EXT CLKFractional baud divisor

instance 2 × clock_source 2 × baud_rates 4 = 16 results

TC_UART_0010 · UART_RX_STATUS_INTERRUPTS

Not implemented

P2plannedowner unassignedrun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

PARITY_ERROR - transmitter sends even parity into a receiver set for odd parity, then odd into even
FRAMING_ERROR - transmitter sends back-to-back frames with 1 stop bit into a receiver set for 2 stop bits
BREAK - transmitter sends a break condition
RX_TIMEOUT - transmitter sends fewer words than the RX watermark and stops; the timeout is timed with SysTick
START_OF_FRAME - transmitter sends single frames with idle gaps between them
Each condition is run UART0 -> UART1 and then UART1 -> UART0

Pass / fail criteria

PARITY_ERROR - parity error flag and interrupt set for each mismatch
FRAMING_ERROR - framing error flag set
BREAK - break flag and interrupt set
RX_TIMEOUT - no RX data interrupt before the timeout; timeout interrupt fires once after the programmed number of bit times; words left in the FIFO read back correctly
START_OF_FRAME - one interrupt per received frame and none while the line is idle
No error flag set when both ends use the same configuration
Expected results = 5 x 2 = 10

Hardware connection

Defined when implemented

Features and configuration

Parity error detectionFraming error detectionBreak detectionReceiver timeout interruptStart-of-frame interrupt

condition 5 × direction 2 = 10 results

TC_UART_0012 · UART_FIFO

Not implemented

P2plannedowner unassignedrun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Each check below is run on UART0 and then on UART1
Fill the TX FIFO with the transmitter disabled and check the TX count at each level
Receive known numbers of words and check the RX count
Flush each FIFO and check its count returns to zero
Step the RX and TX watermarks through their range and check the watermark interrupts

Pass / fail criteria

TX and RX counts match the number of words written or received
A flush empties only the FIFO it targets
Watermark interrupts fire exactly at the programmed level
Expected results = 2 (one per instance)

Hardware connection

Defined when implemented

Features and configuration

FIFO flush RX/TXFIFO count RX/TXFIFO watermark RX/TX

instance 2 = 2 results

TC_UART_0015 · UART_HALF_DUPLEX

In development

P1readyowner Jyeshtarun manualsetup UART_HDX_EARBUD · time tbdexecution tbd

Last runNot run yet

BoardVK001_RevA

Bugsnone

Test description

Single-wire half-duplex exchange with the TWS earbud at the baud rate the customer will use
Repeated for each UART's single-wire pin and each internal pull-up setting
For each run, increase the baud rate until communication fails to find the highest working rate
Capture the waveform and record rise and fall times for each run

Pass / fail criteria

SoC receives the earbud's response without error at the customer baud rate, on both UARTs and every pull-up setting
Highest working baud rate and rise/fall times recorded for each run
Expected results = 2 x 2 = 4

Hardware connection

UART0 single-wire TX/RX on pin 17 (VO_R) <==> TWS earbud UART line
UART1 single-wire TX/RX on pin 16 (VO_L) <==> TWS earbud UART line
Internal pull-up on the single-wire pad (bench test used CRM_IOCTRL5 IOP11CPU1 = 3K3, IOP11CPU0 = 2K2)
Marker GPIO toggled on each received byte; scope on the UART line and the marker GPIO
Common GND connection required

Features and configuration

Single-wire half-duplex with internal pull-up

instance 2 × pull_up 2 = 4 results

TC_UART_0017 · UART_DEEPSLEEP_WAKEUP

In development

P1readyowner Jyeshtarun hostsetup UART_PC_DUAL · time tbdexecution tbd

Last runNot run yet

BoardVK001_RevA

Bugsnone

Test description

Enable UART RX as a deep-sleep wake source and enter deep sleep
PC sends a frame to the sleeping SoC
SoC wakes, receives the frame and logs the result
Done once with the wake frame on UART0 and once on UART1

Pass / fail criteria

SoC wakes from deep sleep on the incoming frame, for each UART
Data received after wake matches what the PC sent
Expected results = 2 (one per instance)

Hardware connection

GPIO_2 UART_0_RX <== 16 (J11) <== PC USB-UART adapter A TX
GPIO_6 UART_1_RX <== 32 (J11) <== PC USB-UART adapter B TX
SOFT UART Logger ==> GPIO_3 20 (J11)
Common GND connection required

Features and configuration

Wake from deep sleep on UART RX

instance 2 = 2 results

TC_UART_0018 · UART_LOAD_STRESS

Not implemented

P2plannedowner unassignedrun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

THROUGHPUT - time the TC_UART_0003 transfer with TX/RX interrupts while the CPU reads and writes 1 KB of SRAM in a loop (X), then with the CPU idle in while(1) (Y); raise the baud rate until data is corrupted
SOAK - UART0 <-> UART1 loopback with pseudo-random data for 1 hour while the CPU keeps the SRAM traffic running

Pass / fail criteria

THROUGHPUT - X - Y within the limit agreed for the SoC; highest error-free baud rate under load recorded
SOAK - zero mismatches over the full hour; total words transferred logged
Expected results = 2

Hardware connection

Defined when implemented

Features and configuration

Throughput under bus-matrix load1-hour PRBS loopback stress

phase 2 = 2 results

TC_UART_0020 · UART_MODE_OPTIONS

Not implemented

P2plannedowner unassignedrun autosetup UART_LOOP_IOSET0 · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

MSB_FIRST - UART0 transmits MSb-first while UART1 receives LSb-first, then both ends MSb-first
POLARITY_INVERTED - invert polarity on one end only, then on both ends
CLK_MUX_BYPASS - run the loopback with the glitch-free mux in use and with the bypass enabled, changing the setting while idle between transfers
Each mode is run UART0 -> UART1 and then UART1 -> UART0

Pass / fail criteria

MSB_FIRST - received words are the bit-reversed TX words when only one end is MSb-first, and match when both are
POLARITY_INVERTED - data matches only when both ends use the same polarity
CLK_MUX_BYPASS - data matches in every setting with no corrupted or extra words around a change
Expected results = 3 x 2 = 6

Hardware connection

Defined when implemented

Features and configuration

MSb-first data orderData polarity inversionGlitch-free clock mux bypass

mode 3 × direction 2 = 6 results

TC_UART_0021 · UART_HW_FLOW_CONTROL

Not implemented

P2plannedowner unassignedrun autosetup UART_FLOW_CTRL · time tbdexecution tbd

Last runPlanned, no code yet

Board-

Bugsnone

Test description

Connect UART0 RTS/CTS to UART1 CTS/RTS
Hold off the receiver and check the transmitter stops while CTS is deasserted
Run UART0 -> UART1 and then UART1 -> UART0

Pass / fail criteria

Transmitter pauses while CTS is deasserted and resumes when it is asserted
No data lost
Expected results = 2 (one per direction)

Hardware connection

Defined when implemented

Features and configuration

Hardware flow control RTS/CTS

direction 2 = 2 results