| TC_ARM_CORE_0001 | - Verify default values of NVIC registers after reset
- Perform random read/write on NVIC registers with mask validation
- Validate interrupt enable/disable register behavior
- Verify default values of System Control Block registers
- Perform masked write/read on SCB registers using zero and dont-care masks
- Validate AIRCR and CCR reset values
- Verify SysTick register default values and 24-bit masking behavior
- Perform masked write/read on SysTick registers
- Verify Debug control register default values
- Validate key-based write access for DHCSR register
- Perform masked write/read on debug registers
- Validate final PASS/FAIL using SRAM_DEBUG2 register
| - | unassigned | PASS 1/1 | 03-Sep-2026 17:11:14 | - - execution tbd |
| TC_ARM_CORE_0002 | - Verify CPUID matches expected value 0x410CC601
- Verify CPUID register is non-zero
- Perform write/read on SysTick CSR register
- Attempt write/read on MPU_TYPE register and check mismatch behavior
- Perform key-based write/read on DHCSR register and validate bit[0]
- Generate PASS/FAIL using trigger_event calls
| - | unassigned | PASS 1/1 | 03-Sep-2026 17:11:35 | - - execution tbd |
| TC_ARM_CORE_0003 | - Write into the systick register and check sys_tick functionality.
| - | unassigned | PASS 1/1 | 03-Sep-2026 17:11:43 | - - execution tbd |
| TC_ARM_CORE_0004 | CORE_INT_EXCEPTIONS_TEST - Create different faults and verify the correct fault handler is invoked.
- Verify proper handling of core exceptions such as HardFault, SVCall, and PendSV.
- Trigger SVCall with priority lower than or equal to the current handler priority and verify it results in a HardFault.
- Trigger SVCall with higher priority than the current handler priority and verify the SVCall handler executes correctly.
| - | unassigned | PASS 1/1 | 07-Sep-2026 19:21:13 | - - execution tbd |
| TC_ARM_CORE_0005 | CORE_INT_NVIC_FEATURES - Verify NVIC features like priority, nesting of interrupts, tail changing.
- Set and clear the Pending interrupt register, and verify pending state before and after reset.
- Trigger Uart interrupt from block level,
- inside uart interrupt handler, trigger GPT0 interrupt.(GPT0 should be serviced immediately as per priority).
- In GPT0 handler trigger I2c, and in I2C trigger pendsv interrupt and then Hardfault(nesting ).
- Verify nesting and tailchanging.
| - | unassigned | PASS 1/1 | 07-Sep-2026 19:21:23 | - - execution tbd |
| TC_ARM_CORE_0006 | CORE_INT_NVIC_INTR - Connectivity of external interrupts( parallel interrup).
- Verify the interrupts from I2C, GPIO, PWM, UART, WDT
- Disable the interrupts in NVIC and Trigger the interrupt from multiple blocks
- Then enable all interrupts through Interrupt Set-Enable Register.
- The external interrupt should be serviced as per the priority level.
- Update the priority and check the order of servicing
- verify pre-empty feature of interrupt.
| - | unassigned | PASS 1/1 | 10-Sep-2026 11:16:42 | - - execution tbd |