CoreMark Test for VAAK001 · UART_EXT_LOOPBACK_IOSET0
In development0/312
owner unassignedexecution tbd
Last run22-Oct-2026 13:26:30
Silicon1.0
BoardVAAK001 RevA
Firmware commit3d89f8f
Bugsnone
Test description
- UART0 TX is externally connected to UART1 RX
- UART1 TX is externally connected to UART0 RX
- Bidirectional UART communication validation is performed
- Data payload size = 64 Bytes
- UART0 RX is interrupt based
- UART1 RX is interrupt based
- Full configuration sweep across baud rate, data width, parity, and stop bits
- Pass/Fail result is logged using Software UART (GPIO3)
Pass / fail criteria
- UART0 RX buffer contents must exactly match UART1 TX buffer
- UART1 RX buffer contents must exactly match UART0 TX buffer
- No data corruption, timeout, or framing errors allowed
Hardware connection
- GPIO_1 UART_0_TX ==>12 (J11) ==> GPIO_6 UART_1_RX ==>32 (J11)
- GPIO_2 UART_0_RX ==>16 (J11) ==> GPIO_5 UART_1_TX ==>28 (J11)
- SOFT UART Logger ==> GPIO_3 20 (J11) GPIO3 is primary function
- Common GND connection required
Features and configuration
External Loopback
baud_rates 13 × data_bits 4 × parity 3 × stop_bits 2 = 312 results