TRGRTR

Test description

• One PRB is tested at a time. It drives TRG_OUT 26, which the SoC feeds back on TRG_IN 27 to a second PRB, the observer, so the observer counts the pulses that come out of the PRB under test
• The observer is the next PRB, (m + 1) mod 8, with the synchronised path, the AHB clock and rising edge detection
• Sources are GPT0 to GPT3 TOUT, PWM0 to PWM3 TOUT, GPT0 to GPT2 TRG_OUT, Hall 0 to 2 pad inputs, TRG_IN 22 to 26 fed back from TRG_OUT 21 to 25, and TRG_IN 12 to 14 from CRM trg_out 3 to 5
• Timer sources make one single pulse mode pulse, Hall sources are driven high then low from GPIO, TRG_IN 22 to 26 are reached by a DRB carrying a GPT3 pulse to TRG_OUT 21 to 25
• For TRG_IN 12 to 14, a DRB carries a GPT3 pulse to TRG_OUT 18 to 20, CRM trg_in 3 to 5, and CRM returns it on trg_out 3 to 5 synchronised to the PWM0 dead-zone clock, with CRM CONFIG2 phase shift bypass set
• The source goes into SRC0 or SRC1, the other slot is 0, and POL inverts the active slot only
• Every combination of PRB, edge, path, clock, source slot and polarity is run once, 512 runs, the source rotates through the list of 22 so every PRB sees every source at least twice
• Source and destination fields are written as signal index + 1
• Routes are configured with interrupts disabled, then STS is cleared and CTRL0 INTEN is set for the PRB under test and the observer, the ISR counts interrupts of each and clears STS by writing 1
• Both counts are taken in the middle of the pulse and again after it, inversion changes which edge comes first so the mid-pulse counts show the polarity
• AHB clock 14.7456 MHz, APB clock half of AHB so the two clock selections differ
• The GPT and PWM clock is set so every timer pulse, including the single mux clock GPT TRG_OUT pulse, is at least two APB clock periods wide

Pass / fail criteria

• One pulse source, not inverted - rising gives 1 at mid-pulse and 1 at the end, falling 0 and 1, both 1 and 2, bypass 0 and 0, for the PRB under test
• One pulse source, inverted - rising gives 0 at mid-pulse and 1 at the end, falling 1 and 1, both 1 and 2, bypass 0 and 0, for the PRB under test
• One pulse source - the observer gives the same mid-pulse and end counts as the PRB under test for rising, falling and both, and for bypass 1 and 1 when not inverted, 0 and 1 when inverted
• GPT TRG_OUT sources make two short pulses - the PRB under test gives 1 at mid-pulse and 2 at the end for rising, falling and both, 0 for bypass, and the observer gives 1 and 2 in every case
• No STS bit other than those of the PRB under test and the observer sets
• Asynchronous path results match synchronised path results

Hardware connection

• None apart from the logger

Features and configuration

prb 8 × edge 4 × path 2 × clock 2 × src_slot 2 × pol 2 = 512 results

Test description

• Covers all 36 TRGRTR registers - CTRL0, CTRL1, STS, DST_POL0, CFG_G0PRB0 to CFG_G0PRB7 and CFG_G0DRB0 to CFG_G0DRB23
• Apply soft reset with CTRL1.SRST and check every register reads its reset value
• Write walking 1s, walking 0s, 0x55555555 and 0xAAAAAAAA patterns to every register and read back
• Write random data to every register and read back
• Apply soft reset, write 0xFF to STS and check every register still reads its reset value
• Write every register with byte and half-word accesses and read back the bytes written
• Write and read a random word address in the unimplemented range 0x4003C0F4 to 0x4003FFFC

Pass / fail criteria

• Every register reads its reset value after soft reset
• RW bits read back the value written for every pattern and for random data
• Reserved bits read 0 after every write, including DST_POL0 bits 31 and 30
• CTRL1 GFB and SRST and STS INT0 are excluded from the pattern and random checks
• Writing 0xFF to STS with no interrupt pending leaves STS at 0
• Byte and half-word writes update only the addressed bytes
• The unimplemented address access raises a HardFault, or reads back 0 when it does not fault

Hardware connection

• None apart from the logger

Features and configuration

1 result

Test description

• One run per router output, 27 runs, each run sets up one DRB only, destination n uses DRB n mod 24 so every DRB is used
• Source and destination fields are written as signal index + 1, the DRB register is SRC or (DST shifted left by 8)
• The pulse source is a GPT3 single pulse of 200 timer clocks, GPT2 for TRG_OUT 3, GPT3 and the destination timers run on the same timer clock
• Every pulse run is repeated with the DRB switched off, and every clock run measures again with the DRB switched off
• TRG_OUT 0 to 3 - GPT3 TOUT to GPT0 to GPT3 gpt_trg_in, destination in standard mode with GPTEN 0, source and destination COUNT read back to back at mid-pulse
• TRG_OUT 4 to 7 - lf100k_clk to GPT0 to GPT3 AUXCLK, DRB written before CLKSEL is set to AUXCLK, DIV 0, counts taken over 10 ms timed by SysTick
• TRG_OUT 8 to 11 - wdt_clk to PWM0 to PWM3 AUXCLK, same method as TRG_OUT 4 to 7, WDT enabled with its longest timeout and cleared in every wait loop
• TRG_OUT 12 to 14 - GPT3 TOUT to SARADC_TRG_IN 0 to 2, ADC set for one hardware triggered conversion on a fixed internal channel
• TRG_OUT 18 to 20 - GPT3 TOUT to CRM trg_in 3 to 5, PWM0 running with a dead zone and CRM CONFIG2 phase shift bypass set, CRM returns the pulse on trg_out 3 to 5, TRG_IN 12 to 14, to observer PRB0 with rising edge detection and its interrupt enabled
• TRG_OUT 21 to 26 - GPT3 TOUT to PWM0 OE0 to OE5, the SoC feeds it back on TRG_IN 22 to 27 to observer PRB0 with rising edge detection and its interrupt enabled
• TRG_OUT 27 to 29 - GPT3 TOUT to PWM1 to PWM3 TIN, PWM in input capture mode
• CTRL0 enables only the observer PRB, and STS is read after every run

Pass / fail criteria

• TRG_OUT 0 to 3 - GPTEN goes from 0 to 1, source COUNT minus destination COUNT at mid-pulse is 0 to 4 timer clocks, and with the DRB off GPTEN stays 0
• TRG_OUT 4 to 7 - 375 to 625 counts in 10 ms with the DRB on, 0 counts in 10 ms with the DRB off
• TRG_OUT 8 to 11 - 115 to 192 counts in 10 ms with the DRB on, 0 counts in 10 ms with the DRB off
• TRG_OUT 12 to 14 - no conversion before the pulse, exactly one conversion after it with a result in the expected range for the channel, none with the DRB off
• TRG_OUT 18 to 26 - the observer counts exactly 1 interrupt, and none more with the DRB off
• TRG_OUT 27 to 29 - INTA and INTB each set once, CNTRB minus CNTRA is 200 plus or minus 2 timer clocks, and no capture with the DRB off
• No STS bit is set by a DRB in any run, only the observer bit for TRG_OUT 18 to 26

Hardware connection

• None apart from the logger

Features and configuration

destination 27 = 27 results

Test description

• Every case uses a route under test that drives TRG_OUT 21, which the SoC feeds back on TRG_IN 22 to observer PRB7
• Observer PRB7 is CFG_G0PRB7 0x00050017 - SRC0 TRG_IN 22, synchronised path, APB clock, rising edge detection, no destination
• Sources are GPT0 and GPT1 TOUT, each making one single pulse of about 217 us, started by the CPU
• Each case - clear all routes, DST_POL0 and STS, write the route under test and the observer, wait, clear STS, enable the interrupts, fire the pulse, read the observer count in the middle of the pulse and after it, then clear DST_POL0 and all routes
• drb_no_inversion - DRB0 0x1601, GPT0 to TRG_OUT 21, GPT0 pulses
• drb_source_inverted - DRB0 0x1621, as drb_no_inversion with POL 1
• destination_inverted - DRB0 0x1601 and DST_POL0 0x00200000
• source_and_destination_inverted - DRB0 0x1621 and DST_POL0 0x00200000
• prb_src0_pulse - PRB0 0x16000201, SRC0 GPT0 and SRC1 GPT1, asynchronous path with edge bypass, to TRG_OUT 21, GPT0 pulses
• prb_src1_pulse - as prb_src0_pulse, GPT1 pulses
• shared_destination_prb_pulse - PRB0 0x16000001 with GPT0 and DRB0 0x1602 with GPT1, both to TRG_OUT 21, GPT0 pulses
• shared_destination_drb_pulse - as shared_destination_prb_pulse, GPT1 pulses
• disabled_source_field - DRB0 0x1600, source field 0 and destination TRG_OUT 21, GPT0 pulses
• disabled_destination_field - DRB0 0x0001, source GPT0 and destination field 0, GPT0 pulses
• prb_destination_field_zero - PRB0 0x00050001, SRC0 GPT0, synchronised path, APB clock, rising edge, destination field 0, PRB0 interrupt enabled too, GPT0 pulses
• prb_disabled - PRB0 0x00050000, source and destination fields 0, PRB0 interrupt enabled too, GPT0 pulses

Pass / fail criteria

• No inversion or two inversions in the path - observer count 1 in the middle of the pulse and 1 after it
• One inversion in the path - observer count 0 in the middle of the pulse and 1 after it
• Either source of a PRB, and either route to a shared destination - observer count 1 in the middle of the pulse and 1 after it
• A disabled DRB source or destination field - observer count 0 during and after the pulse
• prb_destination_field_zero - PRB0 counts 1 interrupt and the observer counts 0
• prb_disabled - PRB0 counts 0 interrupts and the observer counts 0
• No STS bit sets other than bit 7, and bit 0 in the last two cases

Hardware connection

• None apart from the logger

Features and configuration

case 12 = 12 results

Test description

• Program PRB0 with a GPT TOUT source, rising edge detection and its interrupt enabled, with the TRGRTR interrupt disabled in the NVIC
• Send one GPT pulse so STS bit 0 sets and the TRGRTR interrupt is pending in the NVIC
• Write CTRL0, CTRL1 GFB, DST_POL0 and all PRB and DRB configuration registers with the case pattern, STS stays set
• Set CTRL1.SRST
• Read back all 36 registers
• Send one GPT pulse and check no route and no interrupt responds
• Program PRB0 again and send one GPT pulse to check the router works after the soft reset

Pass / fail criteria

• Before SRST every written register reads the case pattern and STS bit 0 is set
• After SRST all 36 registers read their reset values, including STS and CTRL1.SRST
• After SRST the TRGRTR interrupt is no longer pending in the NVIC
• After SRST a GPT pulse sets no STS bit and raises no interrupt
• After reprogramming PRB0 a GPT pulse sets STS bit 0 again

Hardware connection

• None apart from the logger

Features and configuration

pattern 2 = 2 results

Test description

• The CPU sets up each case, CRM WMASK unmasks only the wake sources named for the case, CTRL.LPM selects the mode and the core executes WFI
• GPT2 runs on its own clock in every case as a backup wake source, WMASK bit 2, with a delay longer than the expected wake, so a failing case wakes on GPT2 instead of hanging
• The SoC has one APB bus, so CMS APB is the APB0 clock, switched per mode by CRM CGEN0 APB0_CGEN
• sleep_prb_apb_clock - SLEEP with APB0_CGEN 2, GPT1 keeps running and its TOUT rises after a delay, TRG_IN 1 reaches PRB0 with SRC0 2, synchronised path, rising edge detection, CMS APB and its interrupt enabled, TRGRTR wake request unmasked, WMASK bit 13
• sleep_prb_ahb_clock - as sleep_prb_apb_clock with CMS AHB, the AHB clock is gated in SLEEP
• deep_sleep_prb_wakeup - as sleep_prb_apb_clock in DEEP SLEEP with APB0_CGEN 3, the RC oscillator is off and GPT1 and the TRGRTR run from the low frequency clock
• deep_sleep_prb_no_clock - as deep_sleep_prb_wakeup with APB0_CGEN 2, so the TRGRTR has no clock in DEEP SLEEP
• deep_sleep_drb_lf_clock - DEEP SLEEP with APB0_CGEN 2, DRB0 0x0510 routes lf100k_clk on TRG_IN 15 to GPT0 AUXCLK on TRG_OUT 4, GPT0 with CLKSEL AUXCLK counts to a compare value and its interrupt wakes the SoC, GPT0 wake request unmasked, WMASK bit 0
• deep_sleep_drb_route_off - as deep_sleep_drb_lf_clock with DRB0 0, so GPT0 gets no clock
• After wake the CPU reads CRM CSR.LFSS first, then CRM STS1.LWKRQ and TRGRTR STS, and logs them

Pass / fail criteria

• sleep_prb_apb_clock and deep_sleep_prb_wakeup - LWKRQ shows the TRGRTR wake request, bit 13, and not GPT2
• sleep_prb_ahb_clock - LWKRQ shows GPT2, bit 2, and not the TRGRTR, which together with sleep_prb_apb_clock shows CMS selects a different clock
• deep_sleep_prb_no_clock - LWKRQ shows GPT2 and not the TRGRTR, as the manual says a PRB raises no wake request without its clock
• deep_sleep_drb_lf_clock - LWKRQ shows GPT0, bit 0, and not GPT2, so DRB0 carried lf100k_clk with the RC oscillator off and the APB0 clock gated
• deep_sleep_drb_route_off - LWKRQ shows GPT2 and not GPT0, so the GPT0 wake in deep_sleep_drb_lf_clock came through DRB0
• Every DEEP SLEEP case - CSR.LFSS reads 1 right after wake, which shows DEEP SLEEP was entered
• Only LWKRQ decides which source woke the SoC, TRGRTR STS is logged for information

Hardware connection

• None apart from the logger

Features and configuration

case 6 = 6 results

Test description

• Cases unsafe_sequence_reconfigure, manual_sequence_reconfigure and corrected_sequence_reconfigure make the same false edge, PRB0 POL 0 to 1 on GPT0 TOUT idle low, which makes PRB0 see 0 to 1 without a GPT0 pulse
• Each of the three starts from PRB0 0x16050001 - SRC0 GPT0 TOUT on TRG_IN 0, synchronised path, APB clock, rising edge detection, destination TRG_OUT 21 - with INTEN0 bit 0 set and STS clear
• unsafe_sequence_reconfigure - write PRB0 0x16050021 with the interrupt enabled
• manual_sequence_reconfigure - the manual 17.8.5 order - clear INTEN0 bit 0, clear STS bit 0, write PRB0 0x00050021, write PRB0 0x16050021, read STS, set INTEN0 bit 0
• corrected_sequence_reconfigure - clear INTEN0 bit 0, write PRB0 0x00050021, write PRB0 0x16050021, clear STS bit 0, set INTEN0 bit 0
• After each of the three, one GPT0 pulse is sent, then PRB0 is restored to POL 0 with its interrupt disabled and STS bit 0 cleared
• live_route_add - PRB0 0x00050002 with INTEN0 bit 0 counts a continuous GPT1 TOUT pulse train, GPT1 counts its own pulses with its period interrupt, and DRB0 0x0510 carries lf100k_clk to GPT0 AUXCLK, GPT0 count sampled every 10 ms by SysTick
• live_route_add - meanwhile the CPU 1000 times adds DRB3 0x1C04, GPT3 TOUT to PWM1 TIN on TRG_OUT 27, and PRB3 0x00050003, GPT2 TOUT, with the corrected sequence on PRB3 only, read-modify-write of CTRL0 and STS bit 3 cleared alone, then removes both, GPT2 and GPT3 also run pulse trains, test runs 1 s
• clock_switch_with_gfm - GFB 0, PRB0 0x00050002 with INTEN0 bit 0 counts a continuous GPT1 TOUT pulse train while the CPU switches PRB0 CMS between APB and AHB in a tight loop for 1 s, so the switches land at random points of the pulses
• gfb_bypass_static - GFB 1, both clocks running, PRB0 counts a GPT1 train of 1000 pulses with CMS APB, then CMS is changed with GPT1 stopped and the train is repeated with CMS AHB
• feedback_loop_no_inversion - observer PRB7 0x00070017, TRG_IN 22, synchronised path, APB clock, both edges, INTEN0 bit 7, DRB0 0x1617 routes TRG_IN 22 to TRG_OUT 21 which feeds TRG_IN 22, then DRB1 0x1601 carries one GPT0 pulse to TRG_OUT 21, then DRB0 is switched off
• feedback_loop_inverted - observer PRB7 as above with INTEN0 bit 7 clear, DRB0 0x1637 forms the loop with POL 1 for 1 ms timed by SysTick, then DRB0 is switched off, STS read, cleared and read again
• After each feedback loop case, with DRB0 off and INTEN0 bit 7 set, one GPT0 pulse is sent through DRB1

Pass / fail criteria

• unsafe_sequence_reconfigure - exactly 1 interrupt from the POL write, then exactly 1 from the GPT0 pulse
• manual_sequence_reconfigure - no interrupt from the reconfiguration, then exactly 1 from the GPT0 pulse, if it fails STS sets while INTEN is 0 and manual 17.8.5 must move step 2 after step 4
• corrected_sequence_reconfigure - no interrupt from the reconfiguration, then exactly 1 from the GPT0 pulse
• live_route_add - PRB0 interrupt count equals the GPT1 pulse count, and GPT0 counts 375 to 625 in every 10 ms window
• clock_switch_with_gfm - PRB0 interrupt count equals the GPT1 pulse count, none missed and none extra
• gfb_bypass_static - exactly 1000 PRB0 interrupts with each clock
• feedback_loop_no_inversion - the observer counts 1 after the GPT0 pulse ends, as the loop holds TRG_OUT 21 high, and 2 after DRB0 is switched off
• feedback_loop_inverted - the CPU removes the loop after 1 ms, STS bit 7 is set after the loop and stays 0 once cleared
• Both feedback loop cases - the GPT0 pulse after the loop gives the observer exactly 2 interrupts
• No STS bit sets other than those of the PRBs used in the case

Hardware connection

• None apart from the logger

Features and configuration

case 8 = 8 results

Test description

• The signal generator drives the Hall 0 pad, TRG_IN 19, the CPU only configures the route and PWM0
• The route under test carries TRG_IN 19 to TRG_OUT 25, OE4, which gates PWM0_HI_2 held high, so the GPIO_5 pin shows the router output
• Route paths - drb DRB0 0x1A14, prb_async PRB0 0x1A000014, prb_sync_apb PRB0 0x1A040014, prb_sync_ahb PRB0 0x1A042014, all PRB paths with edge bypass so the output keeps the input pulse shape
• Propagation delay - the generator sends a pulse train, the delay from the CH1 edge to the CH2 edge is measured for rising and falling edges, with scope persistence on so the minimum and maximum delay are read
• Minimum pulse width - the generator pulse width is reduced until GPIO_5 stops showing every pulse
• AHB clock 14.7456 MHz, APB clock half of AHB

Pass / fail criteria

• Every value in the results grid is measured and recorded
• DRB and PRB asynchronous - delay less than one APB clock period, 136 ns, with no spread
• PRB synchronised - delay minus the DRB delay is 2 to 3 periods of the selected clock, so the spread is one period, 136 ns for APB and 68 ns for AHB
• DRB and PRB asynchronous paths pass a pulse shorter than one APB clock period
• PRB synchronised paths pass every pulse longer than one period of the selected clock

Hardware connection

• Signal generator, 0 to 3.3 V pulses ==> VO_R_Csense pad (Hall 0, TRG_IN 19)
• VO_R_Csense pad ==> scope CH1
• GPIO_5 (PWM0_HI_2, Alt2) ==> scope CH2

Features and configuration

path 4 × measurement 2 = 8 results

Test description

• Runs on the buck-boost test board with an adjustable VIN supply, the battery emulator on VBAT, the load banks and a scope
• CRM automatic shutdown (ACIOC, ACVOC and the BOIC control bit) is disabled so only the TRGRTR path can act
• ioc_to_prb - VIN current is raised above 2.5 A, CRM trg_out 0 on TRG_IN 9 reaches PRB0 0x0005000A, synchronised path, APB clock, rising edge detection, INTEN0 bit 0
• voc_to_prb - VIN is raised above 6 V, CRM trg_out 1 on TRG_IN 10 reaches PRB0 0x0005000B
• boic_to_prb - boost output current is raised above 0.7 A, CRM trg_out 2 on TRG_IN 11 reaches PRB0 0x0005000C
• ioc_shutdown_loop - DRB0 0x100A routes TRG_IN 9 to TRG_OUT 15, CRM IOC trg_in, with all TRGRTR interrupts disabled, then the IOC fault is applied
• voc_shutdown_loop - DRB0 0x110B routes TRG_IN 10 to TRG_OUT 16, CRM VOC trg_in, then the VOC fault is applied
• boic_shutdown_loop - DRB0 0x120C routes TRG_IN 11 to TRG_OUT 17, CRM BOIC trg_in, then the BOIC fault is applied
• In the shutdown loop cases the scope measures the time from the fault to the switch turning off

Pass / fail criteria

• In each to_prb case the PRB0 STS bit sets, the TRGRTR interrupt is raised once, the matching CRM STS fault bit is set, and no other TRGRTR STS bit sets
• ioc_shutdown_loop clears only MCTRL VINEN and BCEN
• voc_shutdown_loop clears only MCTRL VINEN
• boic_shutdown_loop clears only MCTRL V1EN1, V1EN2, V2EN1, V2EN2 and BOEN
• In each shutdown loop case the switch turns off faster than the CRM automatic shutdown for the same fault

Hardware connection

• Adjustable bench supply with current limit ==> USB_VIN
• Battery emulator ==> VBAT
• Load bank ==> VBOOST, for the BOIC cases
• Scope CH1 ==> fault stimulus, VIN voltage or the rail current shunt
• Scope CH2 ==> switched rail of the case

Features and configuration

case 6 = 6 results

Test description

• all_prb_distinct_sources - all 8 PRBs and 8 DRBs run at the same time for 10 s
• DRB0 to DRB3, 0x0510 0x0610 0x0710 0x0810, carry lf100k_clk on TRG_IN 15 to GPT0 to GPT3 AUXCLK, DRB4 to DRB7, 0x0909 0x0A09 0x0B09 0x0C09, carry wdt_clk on TRG_IN 8 to PWM0 to PWM3 AUXCLK, so one source fans out to four DRBs
• The 4 GPTs and 4 PWMs are the 8 pulse sources, GPT0 to GPT3 and PWM0 to PWM3 run in PWM mode on AUXCLK with DIV 0 and make continuous pulse trains, GPT periods 23, 29, 31 and 37 timer clocks, PWM periods 11, 13, 17 and 19 timer clocks, so the edges of different timers drift past each other and sometimes coincide
• Each GPT and PWM counts its own pulses with its period interrupt
• PRB m takes TRG_IN m, GPT0 to GPT3 TOUT and PWM0 to PWM3 TOUT, with the synchronised path and rising edge detection, even PRBs on the APB clock and odd PRBs on the AHB clock - PRB0 0x00050001, PRB1 0x00052002, PRB2 0x00050003, PRB3 0x00052004, PRB4 0x00050005, PRB5 0x00052006, PRB6 0x00050007, PRB7 0x00052008
• all_prb_same_source - all 8 PRBs take GPT0 TOUT on TRG_IN 0, even PRBs 0x00050001 on the APB clock and odd PRBs 0x00052001 on the AHB clock, GPT0 in PWM mode on its normal clock makes 1000 pulses of a 200 us period and stops itself, counted by its own interrupt
• In both cases CTRL0 INTEN is 0xFF, one TRGRTR ISR counts each STS bit it reads and clears only those bits
• The TRGRTR interrupt has the lowest priority and the GPT and PWM interrupts a higher one, so the TRGRTR ISR is serviced last and can be interrupted between reading and clearing STS
• Each ISR updates only its own counters, the main loop reads them after all sources have stopped, the 10 s run is timed by polling SysTick without its interrupt
• The counts of every PRB and timer are logged before each TEST_RESULT, in all_prb_same_source also the number of TRGRTR ISR entries and of STS reads equal to 0xFF

Pass / fail criteria

• all_prb_distinct_sources - every PRB interrupt count equals the pulse count of its source timer, none missed and none extra
• all_prb_distinct_sources - every timer pulse count is within 25 percent of 10 s times half its AUXCLK frequency divided by its period, which shows every DRB delivered its clock for the whole run
• all_prb_same_source - every PRB counts exactly 1000 interrupts
• STS reads 0 at the end of each case

Hardware connection

• None apart from the logger

Features and configuration

case 2 = 2 results