TC_TRGRTR_0002 · TRGRTR_REG_RW
TRGRTR ยท TRGRTR
PASS
1 passed · 0 failed · 1 of 1 expected results
Open issues
- Unimplemented address check passes whether or not a HardFault occurs. Change the code to require the HardFault so PSLVERR is proven
- Unimplemented address check starts at 0x4003C0F4. Extend it to cover 0x4003C09C to 0x4003C0F0
Features
Register reset valuesRegister access
Test description
- Covers all 36 TRGRTR registers - CTRL0, CTRL1, STS, DST_POL0, CFG_G0PRB0 to CFG_G0PRB7 and CFG_G0DRB0 to CFG_G0DRB23
- Apply soft reset with CTRL1.SRST and check every register reads its reset value
- Write walking 1s, walking 0s, 0x55555555 and 0xAAAAAAAA patterns to every register and read back
- Write random data to every register and read back
- Apply soft reset, write 0xFF to STS and check every register still reads its reset value
- Write every register with byte and half-word accesses and read back the bytes written
- Write and read a random word address in the unimplemented range 0x4003C0F4 to 0x4003FFFC
Pass / fail criteria
- Every register reads its reset value after soft reset
- RW bits read back the value written for every pattern and for random data
- Reserved bits read 0 after every write, including DST_POL0 bits 31 and 30
- CTRL1 GFB and SRST and STS INT0 are excluded from the pattern and random checks
- Writing 0xFF to STS with no interrupt pending leaves STS at 0
- Byte and half-word writes update only the addressed bytes
- The unimplemented address access raises a HardFault, or reads back 0 when it does not fault
Results
| Configuration | Result |
|---|---|
| Patters Checked = Default, Walking_1s, Walking_0s, Walking_5s, Walking_As & Random | PASS |