NVMC

Test description

• 32-bit Access
• Verify RW on all CSRs
• Write patterns (all 1s/0s, 55/AA, walking 1/0)
• Read & compare error on mismatch
• Default Check
• Read CSRs after reset
• Compare with reset values
• Ensure STS, RED, DCT are read-only
• Invalid Address:Access out-of-range → check HRESP
• 8/16-bit Access,Write 32-bit, read byte,halfword,Compare (ignore reserved/reset bits)
• Unimplemented Addr
• Verify HRESP assertion
• Pre-reset:Check register values before reset

Pass / fail criteria

Hardware connection

• NVMC register read/write validation is executed from firmware
• Default register values are verified after reset
• Register pattern testing is performed on CTRL,
• Random data write/read verification is performed
• Byte, half-word, and word accesses are validated using hsize/pstrb checks
• Invalid and out-of-range address accesses are also tested
• Test includes multiple reset scenarios (C_RESET1 to C_RESET7)
• Test execution is marked with START and END events

Features and configuration

1 result

Test description

• Intention of the test is to check whether the NVMC interrupt is generated and serviced. For write and erase completion, single bit and double bit error, and water mark level
• Set Fuse bits LDT0[117] to enable erase operation as in control register.
• Enable all the interrupts by configuring in control register.
• set watermark level to get WRD flag.
• after erase operation enter wfi mode and wait for ERC interrupt.
• perform read operation without write to get SBE.
• perform write operation to flash and enter wfi mode, to get WRC interrupt.
• deposit another value to the write loaction through backdoor and perform read to that location to get DBE/SBE.

Pass / fail criteria

Hardware connection

• The connections are made on the ATE board.
• GPIO_3 (logger) ==> J2(19) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result

Test description

• Intention of the test is to verify NVMC erase, write and read operations
• Set Fuse bits LDT0[117] and LDT0[126] to enable erase operation and Boot protection
• Configure erase_sel for page erase and enable boot protection
• Perform matrix erase operation and check MAS and BBLOCKEN behavior
• Initiate AHB write operation and wait for interrupt using WFI
• Read back data and compare with expected values

Pass / fail criteria

Hardware connection

• The connections are made on the ATE board.
• GPIO_3 (logger) ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result

Test description

• Clear NVMC status register bits before starting test
• Configure NVMC control register with WRWM, BPEN, WRCIEN, WRDIEN
• Read all flash locations before erase for observation
• Perform page erase using control register
• Wait for erase completion using status register polling
• Verify all flash locations are erased (expect 0xFFFFFFFF)
• Perform burst write of data in chunks of 8 words
• Clear first write complete status during burst sequence
• Wait for write completion using status register
• Repeat burst programming across memory regions
• Verify programmed data matches expected pattern (0xA0 + index)
• Generate PASS/FAIL using trigger_event calls

Pass / fail criteria

Hardware connection

• The connections are made on the ATE board.
• GPIO_3 (logger) ==> J2(19) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result