VK001 Post-Si ValidationHW101x · silicon 1.0
Dashboard / SRAM

SRAM

3 test cases · SRAM · silicon 1.0 · generated 02-Nov-2026 14:11:07

PASS 3
No priority set3 of 3 passed · 0 not passed
Bench time (estimates)
TestsExecution (min – max)Setup (min – max)Total (min – max)Estimated
All tests3tbd-tbd0 of 3 tests
Not passed0---0 of 0 tests
Feature coverage · 2 features · 2 verified · 0 failing · 0 open
FeatureCovered byFeature status
SRAM Error Handling, Reset Validation & Data Integrity Check
0001
PASS
Memory Read/Write
00020003
PASS

Test cases

3 of 3 shown
Priority
Status
Test caseName and test descriptionPriorityOwnerStatusLast runRun mode · setup · execution
TC_SRAM_0001
SRAMC_ERROR_TEST
  • Execute test under C_RESET1 and C_RESET2 conditions
  • In C_RESET1, force failure path to validate error/reset handling
  • In C_RESET2, perform write and read-back validation of SRAM location
  • Compare read data against expected value to ensure data integrity
  • Validate correct behavior during reset and error scenarios
  • Trigger PASS on successful validation and FAIL on mismatch
  • Ensure proper test sequencing using START and END events
-unassignedPASS
1/1
03-Sep-2026 17:28:20
-
-
execution tbd
TC_SRAM_0002
SRAM_MEMORY_REG_READ_WRITE
  • Write entire memory using random data with different sizes (word).
  • Perform random read/write sequences (back-to-back, with/without idle cycles).
  • Verify pipeline operation and basic transfer types.
  • Use a self-checking testbench to validate data and give pass/fail
-unassignedPASS
1/1
02-Sep-2026 19:15:14
-
-
execution tbd
TC_SRAM_0003
SRAM_MEMORY_BYTE_HALFWORD_WORD_READ_WRITE
  • Write SRAM using random byte (8-bit) data and verify readback.
  • Write SRAM using random halfword (16-bit) data and verify readback.
  • Write SRAM using random word (32-bit) data and verify readback.
  • Perform back-to-back read/write sequences.
  • Verify basic memory transfer operations for byte, halfword and word accesses.
  • Use a self-checking testbench to validate data and give pass/fail.
-unassignedPASS
1/1
17-Sep-2026 16:52:00
-
-
execution tbd

TC_SRAM_0001 · SRAMC_ERROR_TEST

PASS1/1
owner unassignedexecution tbd
Last run03-Sep-2026 17:28:20
Silicon1.0
BoardVAAK001 RevA
Firmware commitunknown
Bugsnone
Filesreport · log

Test description

  • Execute test under C_RESET1 and C_RESET2 conditions
  • In C_RESET1, force failure path to validate error/reset handling
  • In C_RESET2, perform write and read-back validation of SRAM location
  • Compare read data against expected value to ensure data integrity
  • Validate correct behavior during reset and error scenarios
  • Trigger PASS on successful validation and FAIL on mismatch
  • Ensure proper test sequencing using START and END events

Pass / fail criteria

-

Hardware connection

  • The connections are made on the ATE board.
  • logger GPIO3 ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

SRAM Error Handling, Reset Validation & Data Integrity Check

1 result

TC_SRAM_0002 · SRAM_MEMORY_REG_READ_WRITE

PASS1/1
owner unassignedexecution tbd
Last run02-Sep-2026 19:15:14
Silicon1.0
BoardVAAK001 RevA
Firmware commitunknown
Bugsnone
Filesreport · log

Test description

  • Write entire memory using random data with different sizes (word).
  • Perform random read/write sequences (back-to-back, with/without idle cycles).
  • Verify pipeline operation and basic transfer types.
  • Use a self-checking testbench to validate data and give pass/fail

Pass / fail criteria

-

Hardware connection

  • The connections are made on the ATE board.
  • logger GPIO3 ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

Memory Read/Write

1 result

TC_SRAM_0003 · SRAM_MEMORY_BYTE_HALFWORD_WORD_READ_WRITE

PASS1/1
owner unassignedexecution tbd
Last run17-Sep-2026 16:52:00
Silicon1.0
BoardVAAK001 RevA
Firmware commitunknown
Bugsnone
Filesreport · log

Test description

  • Write SRAM using random byte (8-bit) data and verify readback.
  • Write SRAM using random halfword (16-bit) data and verify readback.
  • Write SRAM using random word (32-bit) data and verify readback.
  • Perform back-to-back read/write sequences.
  • Verify basic memory transfer operations for byte, halfword and word accesses.
  • Use a self-checking testbench to validate data and give pass/fail.

Pass / fail criteria

-

Hardware connection

  • The connections are made on the ATE board.
  • logger GPIO3 => J1(21) => USB-to-UART(TX) => PC

Features and configuration

Memory Read/Write

1 result

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