GPIO

Test description

• Read all registers and check the default value is matching with read value.
• Status of GPIO STS register(0x08) depends on the events on the pins.
• Write the read only registers and read it back and it should have only default value.
• Read the Write only registers and it should have default value.
• write and read all RW registers and check the write data is matching with read data - pattern check.
• write and read all RW registers and check the write data is matching with read data - random data check.
• write and read unimplemented address as 0x4002_8000 to 0x4002_BFFF is the allocated range for GPIO and 0x00 to 0x24 and check DUT is issuing plsverr.
• check write and read to all register for all byte and half word combinations of hsize and check the generation of pstrb according to hsize.
• Configure different hprot from ARM Core and Initiate write and read to GPIO with pprot with different access like privileged and user access then see nothing reflects on read and write
• Test is considered PASS only if no FAIL event occurs.

Pass / fail criteria

Hardware connection

• GPIO register read/write validation is executed from firmware
• Default register values are verified after reset
• Register pattern testing is performed on CTRL,INTSET0,INTSET1,STS,DIR,OUT
• Random data write/read verification is performed
• Byte, half-word, and word accesses are validated using hsize/pstrb checks
• Invalid and out-of-range address accesses are also tested
• Test includes multiple reset scenarios (C_RESET1 to C_RESET5)
• Test execution is marked with START and END events

Features and configuration

1 result

Test description

• 6 GPIOs loopback to other 6 GPIO from the pad.
• 6 configured as Input & 6 as output & cover A5A5 pattern, walking 1 pattern, walking 0 pattern on these pads.
• Then reverse the configuration to make input pad as output & output as input & cover cover A5A5 pattern, walking 1 pattern, walking 0 pattern.

Pass / fail criteria

Hardware connection

• loopback connection- 1 -> 6, 2 -> 7, 4 -> 8, 5 -> 9, 13 -> 11, 14 -> 12

Features and configuration

1 result

Test description

• 6 GPIOs loopback to other 6 GPIO from the pad.
• 6 configured as Input & 6 as output
• Enable different configurations of interrupt like level or edge interrupts on different GPIO.
• After configuring write values to output pins according to their configuration and see the interrupt and clear the interrupt in the corresponding input pin.

Pass / fail criteria

Hardware connection

• loopback connection- 1 -> 6, 2 -> 7, 4 -> 8, 5 -> 9, 13 -> 11, 14 -> 12

Features and configuration

1 result

Test description

• GPIO interrupt generation and low power mode wake-up are validated from firmware.
• CRM registers are configured for ALT0 pin muxing and IO control.
• GPIO direction is configured (Pin 1 as input, Pin 6 as output).
• System enters Sleep Mode (LPM_SLEEP_MODE) and waits for interrupt (WFI).
• Wakeup is triggered via GPIO interrupt (Level High).
• Interrupt handler verifies the status register, increments pass/fail counters, and clears the interrupt.

Pass / fail criteria

Hardware connection

• GPIO 13 => Before entering Sleep Mode, GPIO 13 is configured as input with pull-up resistor.After entering Sleep Mode, GPIO 13 is pulled low to generate interrupt and wake up the system.

Features and configuration

1 result