PWM

12 test cases · PWM_0, PWM_1, PWM_2, PWM_3 · silicon 1.0 · generated 02-Nov-2026 14:11:07

PASS 12

No priority set12 of 12 passed · 0 not passed

Bench time (estimates)

	Tests	Execution (min – max)	Setup (min – max)	Total (min – max)	Estimated
All tests	12	tbd	-	tbd	0 of 12 tests
Not passed	0	-	-	-	0 of 0 tests

Feature coverage · 3 features · 3 verified · 0 failing · 0 open

Feature	Covered by	Feature status
Register Read Write	0001 0002 0003 0004	PASS
Duty Cycle Mode	0005 0006 0007 0008	PASS
Maximum Frequency	0013 0014 0015 0016	PASS

Test cases

12 of 12 shown

Priority

Status

Test case	Name and test description	Priority	Owner	Status	Last run	Run mode · setup · execution
TC_PWM_0001	PWM_0_REG_RW Verify default register values after reset Pattern write/read verification on RW registers Read-only register validation Reserved bits write protection check across registers Random read/write validation on RW registers Invalid address access generates PSLVERR Byte, half-word, and word access verification (hsize/pstrb) Multi-reset sequence validation (C_RESET1 to C_RESET3)	-	unassigned	PASS 1/1	03-Sep-2026 17:27:23	- - execution tbd
TC_PWM_0002	PWM_1_REG_RW Verify default register values after reset Pattern write/read verification on RW registers Read-only register validation for GPT_STS and GPT_COUNT Reserved bits write protection check across registers Random read/write validation on RW registers Invalid address access generates PSLVERR Byte, half-word, and word access verification (hsize/pstrb) Multi-reset sequence validation (C_RESET1 to C_RESET3)	-	unassigned	PASS 1/1	03-Sep-2026 17:27:33	- - execution tbd
TC_PWM_0003	PWM_2_REG_RW Verify default register values after reset Pattern write/read verification on RW registers Read-only register validation for GPT_STS and GPT_COUNT Reserved bits write protection check across registers Random read/write validation on RW registers Invalid address access generates PSLVERR Byte, half-word, and word access verification (hsize/pstrb) Multi-reset sequence validation (C_RESET1 to C_RESET3)	-	unassigned	PASS 1/1	03-Sep-2026 17:27:40	- - execution tbd
TC_PWM_0004	PWM_3_REG_RW Verify default register values after reset Pattern write/read verification on RW registers Read-only register validation for GPT_STS and GPT_COUNT Reserved bits write protection check across registers Random read/write validation on RW registers Invalid address access generates PSLVERR Byte, half-word, and word access verification (hsize/pstrb) Multi-reset sequence validation (C_RESET1 to C_RESET3)	-	unassigned	PASS 1/1	03-Sep-2026 17:27:46	- - execution tbd
TC_PWM_0005	PWM_0_PWM_MODE_DC_TEST Check that the pins intended for PWM_0 are configured to ALT0 mode through IO Muxing The test intent is to verify gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB. The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set . The above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%	-	unassigned	PASS 1/1	02-Sep-2026 19:18:00	- - execution tbd
TC_PWM_0006	PWM_1_PWM_MODE_DC_TEST Check that the pins intended for PWM_1 are configured to ALT1 mode through IO Muxing The test intent is to verify gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB. The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set . The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set . If the counters are not programmed with new values after counter rollover check EXPA and EXPB is raised or not if CNTRAEN & CNTRBEN is Set. ThThe above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%	-	unassigned	PASS 1/1	02-Sep-2026 19:18:10	- - execution tbd
TC_PWM_0007	PWM_2_PWM_MODE_DC_TEST Check that the pins intended for PWM_2 are configured to ALT1 mode through IO Muxing The test intent is to verify gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB. The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set . The above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%	-	unassigned	PASS 1/1	02-Sep-2026 19:18:17	- - execution tbd
TC_PWM_0008	PWM_3_PWM_MODE_DC_TEST The test intent is to verify gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB. The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set The above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%	-	unassigned	PASS 1/1	07-Sep-2026 15:18:45	- - execution tbd
TC_PWM_0013	PWM_0_MAX_FREQUENCY_TEST Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7. Generate PWM output with 50% duty cycle. Verify PWM0 tout signal frequency. Verify INTA, INTB, EXPA and EXPB generation. Verify interrupt status clearing. Report PASS/FAIL based on expected behavior.	-	unassigned	PASS 1/1	23-Sep-2026 15:49:20	- - execution tbd
TC_PWM_0014	PWM_1_MAX_FREQUENCY_TEST Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7. Generate PWM output with 50% duty cycle. Verify PWM0 tout signal frequency. Verify INTA, INTB, EXPA and EXPB generation. Verify interrupt status clearing. Report PASS/FAIL based on expected behavior.	-	unassigned	PASS 1/1	23-Sep-2026 15:49:11	- - execution tbd
TC_PWM_0015	PWM_2_MAX_FREQUENCY_TEST Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7. Generate PWM output with 50% duty cycle. Verify PWM0 tout signal frequency. Verify INTA, INTB, EXPA and EXPB generation. Verify interrupt status clearing. Report PASS/FAIL based on expected behavior.	-	unassigned	PASS 1/1	23-Sep-2026 15:49:27	- - execution tbd
TC_PWM_0016	PWM_3_MAX_FREQUENCY_TEST Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7. Generate PWM output with 50% duty cycle. Verify PWM0 tout signal frequency. Verify INTA, INTB, EXPA and EXPB generation. Verify interrupt status clearing. Report PASS/FAIL based on expected behavior.	-	unassigned	PASS 1/1	23-Sep-2026 15:49:36	- - execution tbd

TC_PWM_0001 · PWM_0_REG_RW

PASS1/1

owner unassignedexecution tbd

Last run03-Sep-2026 17:27:23

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Verify default register values after reset
Pattern write/read verification on RW registers
Read-only register validation
Reserved bits write protection check across registers
Random read/write validation on RW registers
Invalid address access generates PSLVERR
Byte, half-word, and word access verification (hsize/pstrb)
Multi-reset sequence validation (C_RESET1 to C_RESET3)

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
GPIO_3 (logger) ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result

TC_PWM_0002 · PWM_1_REG_RW

PASS1/1

owner unassignedexecution tbd

Last run03-Sep-2026 17:27:33

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Verify default register values after reset
Pattern write/read verification on RW registers
Read-only register validation for GPT_STS and GPT_COUNT
Reserved bits write protection check across registers
Random read/write validation on RW registers
Invalid address access generates PSLVERR
Byte, half-word, and word access verification (hsize/pstrb)
Multi-reset sequence validation (C_RESET1 to C_RESET3)

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
GPIO_3 (logger) ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result

TC_PWM_0003 · PWM_2_REG_RW

PASS1/1

owner unassignedexecution tbd

Last run03-Sep-2026 17:27:40

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Verify default register values after reset
Pattern write/read verification on RW registers
Read-only register validation for GPT_STS and GPT_COUNT
Reserved bits write protection check across registers
Random read/write validation on RW registers
Invalid address access generates PSLVERR
Byte, half-word, and word access verification (hsize/pstrb)
Multi-reset sequence validation (C_RESET1 to C_RESET3)

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
GPIO_3 (logger) ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result

TC_PWM_0004 · PWM_3_REG_RW

PASS1/1

owner unassignedexecution tbd

Last run03-Sep-2026 17:27:46

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Verify default register values after reset
Pattern write/read verification on RW registers
Read-only register validation for GPT_STS and GPT_COUNT
Reserved bits write protection check across registers
Random read/write validation on RW registers
Invalid address access generates PSLVERR
Byte, half-word, and word access verification (hsize/pstrb)
Multi-reset sequence validation (C_RESET1 to C_RESET3)

Pass / fail criteria

Hardware connection

['The connections are made on the ATE board.']
GPIO_3 (logger) ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

1 result

TC_PWM_0005 · PWM_0_PWM_MODE_DC_TEST

PASS1/1

owner unassignedexecution tbd

Last run02-Sep-2026 19:18:00

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Check that the pins intended for PWM_0 are configured to ALT0 mode through IO Muxing
The test intent is to verify
gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB.
The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set
The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set .
The above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
LED0 (PWM0) ==> J1 (19) ==> Logic Analyzer - Displays gpt0 tout signal.
GPIO_13(VO_R_SENSE) ==> TP4 ==> Logic Analyzer - Displays gpt0 tout signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays interrupt signal.
logger GPIO3 ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

Duty Cycle Mode

1 result

TC_PWM_0006 · PWM_1_PWM_MODE_DC_TEST

PASS1/1

owner unassignedexecution tbd

Last run02-Sep-2026 19:18:10

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Check that the pins intended for PWM_1 are configured to ALT1 mode through IO Muxing
The test intent is to verify
gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB.
The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set .
The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set .
If the counters are not programmed with new values after counter rollover check EXPA and EXPB is raised or not if CNTRAEN & CNTRBEN is Set.
ThThe above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
LED1 (PWM1) ==> J1 (07) ==> Logic Analyzer - Displays gpt1 tout signal.
GPIO_13(VO_R_SENSE) ==> TP4 ==> Logic Analyzer - Displays interrupt signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays gpt1 tout signal
logger GPIO3 ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

Duty Cycle Mode

1 result

TC_PWM_0007 · PWM_2_PWM_MODE_DC_TEST

PASS1/1

owner unassignedexecution tbd

Last run02-Sep-2026 19:18:17

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Check that the pins intended for PWM_2 are configured to ALT1 mode through IO Muxing
The test intent is to verify
gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB.
The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set
The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set .
The above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
LED2 (PWM2) ==> J1 (09) ==> Logic Analyzer - Displays gpt2 tout signal.
PWM2 (TEMP) ==> TP3 ==> Logic Analyzer - Displays gpt2 tout signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays interrupt signal.
logger GPIO3 ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

Duty Cycle Mode

1 result

TC_PWM_0008 · PWM_3_PWM_MODE_DC_TEST

PASS1/1

owner unassignedexecution tbd

Last run07-Sep-2026 15:18:45

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

The test intent is to verify
gpt output,tout toggle or not when the counter reaches programmed value of CNTRA and it toggle again when the counter reaches programmed value of CNTRB.
The interrupt,INTA(gpt_int[0]) is raised or not when the counter reaches programmed value of CNTRA if INTAEN bit is set
The interrupt,INTB(gpt_int[1]) is raised or not when the counter reaches programmed value of CNTRB if INTBEN bit is set
The above mentioned steps should be repeated for different duty cycles like 1%->25%->50%->90%->99.9%

Pass / fail criteria

Hardware connection

['The connections are made on the ATE board.']
LED3 (PWM3) ==> J15 (02) ==> Logic Analyzer - Displays tout signal.
PWM3 (VBAT_CSENSE) ==> TP8 ==> Logic Analyzer - Displays tout signal.
GPIO_14 (VOL_CSENSE) ==> J1 (13) ==> Logic Analyzer - Displays interrupt signal.
logger GPIO3 ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

Duty Cycle Mode

1 result

TC_PWM_0013 · PWM_0_MAX_FREQUENCY_TEST

PASS1/1

owner unassignedexecution tbd

Last run23-Sep-2026 15:49:20

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7.
Generate PWM output with 50% duty cycle.
Verify PWM0 tout signal frequency.
Verify INTA, INTB, EXPA and EXPB generation.
Verify interrupt status clearing.
Report PASS/FAIL based on expected behavior.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
LED0 (PWM0) => J1 (19) => Logic Analyzer - Displays PWM0 tout signal.
GPIO_13 (VO_R_SENSE) => TP4 => Logic Analyzer - Displays PWM0 interrupt signal.
GPIO_14 (VOL_CSENSE) => J1 (13) => Logic Analyzer - Displays interrupt signal.
logger GPIO3 => J1 (21) => USB-to-UART(TX) => PC

Features and configuration

Maximum Frequency

1 result

TC_PWM_0014 · PWM_1_MAX_FREQUENCY_TEST

PASS1/1

owner unassignedexecution tbd

Last run23-Sep-2026 15:49:11

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7.
Generate PWM output with 50% duty cycle.
Verify PWM0 tout signal frequency.
Verify INTA, INTB, EXPA and EXPB generation.
Verify interrupt status clearing.
Report PASS/FAIL based on expected behavior.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
LED1 (PWM1) => Logic Analyzer - Displays PWM1 tout signal.
GPIO configured for PWM1 interrupt => Logic Analyzer - Displays PWM1 interrupt signal.
logger GPIO3 => J1 (21) => USB-to-UART(TX) => PC

Features and configuration

Maximum Frequency

1 result

TC_PWM_0015 · PWM_2_MAX_FREQUENCY_TEST

PASS1/1

owner unassignedexecution tbd

Last run23-Sep-2026 15:49:27

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7.
Generate PWM output with 50% duty cycle.
Verify PWM0 tout signal frequency.
Verify INTA, INTB, EXPA and EXPB generation.
Verify interrupt status clearing.
Report PASS/FAIL based on expected behavior.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
PWM2 output => Logic Analyzer - Displays PWM2 tout signal.
GPIO configured for PWM2 interrupt => Logic Analyzer - Displays PWM2 interrupt signal.
logger GPIO3 => J1 (21) => USB-to-UART(TX) => PC

Features and configuration

Maximum Frequency

1 result

TC_PWM_0016 · PWM_3_MAX_FREQUENCY_TEST

PASS1/1

owner unassignedexecution tbd

Last run23-Sep-2026 15:49:36

Silicon1.0

BoardVAAK001 RevA

Firmware commitunknown

Bugsnone

Filesreport · log

Test description

Configure PWM0 with DIV = 3, CNTRA = 3 and CNTRB = 7.
Generate PWM output with 50% duty cycle.
Verify PWM0 tout signal frequency.
Verify INTA, INTB, EXPA and EXPB generation.
Verify interrupt status clearing.
Report PASS/FAIL based on expected behavior.

Pass / fail criteria

Hardware connection

The connections are made on the ATE board.
PWM3 output => Logic Analyzer - Displays PWM3 tout signal.
GPIO configured for PWM3 interrupt => Logic Analyzer - Displays PWM3 interrupt signal.
logger GPIO3 => J1 (21) => USB-to-UART(TX) => PC

Features and configuration

Maximum Frequency

1 result