VK001 Post-Si ValidationHW101x · silicon 1.0

Needs Attention

39 test cases · generated 02-Nov-2026 14:11:07

GPT 21NVMC 1SARADC 3TRGRTR 9UART 2VAAK SoC 1WDT 2

GPT · 21 tests

Test caseNameCategoryReasonsLast run resultPriorityOwner
TC_GPT_0007GPT2_PWM_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0008GPT3_PWM_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0015GPT2_SINGLE_PULSE_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0016GPT2_SINGLE_PULSE_MODE_CLEAR_SPSOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0017GPT2_SINGLE_PULSE_MODE_CNTRAOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0018GPT3_SINGLE_PULSE_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0019GPT3_SINGLE_PULSE_MODE_CLEAR_SPSOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0020GPT3_SINGLE_PULSE_MODE_CNTRAOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0024GPT2_STD_TIMER_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP1Chandana
TC_GPT_0025GPT3_STD_TIMER_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP1Chandana
TC_GPT_0027GPT2_COMPARE_MATCH_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0029GPT3_COMPARE_MATCH_MODEOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP2Chandana
TC_GPT_0032GPT2_STD_TIMER_MODE_LFOSCOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP1Chandana
TC_GPT_0033GPT3_STD_TIMER_MODE_LFOSCOpen issues
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP1Chandana
TC_GPT_0034GPT3_LPM_MODEOpen issues
  • Open issue: Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP1Chandana
TC_GPT_0035GPT0_LPM_MODEOpen issues
  • Open issue: Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.
PASSP1Chandana
TC_GPT_0036GPT1_LPM_MODEOpen issues
  • Open issue: Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.
PASSP1Chandana
TC_GPT_0037GPT2_LPM_MODEOpen issues
  • Open issue: Excel reports a logic error found in this test at the internal sync-up. The PASS is not confirmed until the code is reviewed and the test is rerun.
  • Open issue: Confirm the logger pin. The Makefile builds this test with LOGGER_UART_ID=0 (UART0), but the old YAML gave the logger as GPIO5 (UART1 TX, also the GPT2 TOUT pin). Check which pad logger_init() uses for UART0 TX (GPIO1 or GPIO3) and that it reaches J1(21), then correct hardware_connection and remove this issue.
PASSP1Chandana
TC_GPT_0021GPT0_GPT1_Cascade_testPlan mismatch
  • test_case_id also used by system_usecases_tests/soc_sram_stress_test, system_usecases_tests/vaak_gpt0_gpt1_cascade_test
Not run-unassigned
TC_GPT_0021GPT0_GPT1_Cascade_testPlan mismatch
  • test_case_id also used by system_usecases_tests/led_brightness_pwm_test, system_usecases_tests/vaak_gpt0_gpt1_cascade_test
Not run-unassigned
TC_GPT_0021GPT0_GPT1_Cascade_testPlan mismatch
  • test_case_id also used by system_usecases_tests/led_brightness_pwm_test, system_usecases_tests/soc_sram_stress_test
PASS-unassigned

NVMC · 1 test

Test caseNameCategoryReasonsLast run resultPriorityOwner
TC_NVMC_0001NVMC_REG_READ_WRITERun not finished
  • Run did not finish: runtime.log has no TEST_RESULT lines
No verdict-unassigned

SARADC · 3 tests

Test caseNameCategoryReasonsLast run resultPriorityOwner
TC_SARADC_0002SARADC_REG_RWRun not finished
  • Run did not finish: runtime.log has no TEST_RESULT lines
No verdict-unassigned
TC_SARADC_0003SARADC_ADCEN_READBACKPlan mismatch
  • test_case_id also used by saradc_tests/adcen_readback_test/adcen_readback_test
Not run-unassigned
TC_SARADC_0003SARADC_ADCEN_READBACKPlan mismatch
  • test_case_id also used by saradc_tests/adcen_readback_test
Not run-unassigned

TRGRTR · 9 tests

Test caseNameCategoryReasonsLast run resultPriorityOwner
TC_TRGRTR_0001TRGRTR_PRB_ROUTINGOpen issues
  • Open issue: Confirm whether the asynchronous path with edge detection sets STS and raises the interrupt, section 17.6.2.2.2 contradicts Figure 54
  • Open issue: Check whether a Hall pad configured as GPIO output drives its own input buffer, else add a GPIO to Hall pad wiring setup
  • Open issue: TRG_IN 28 to 30 carry the SARADC back-EMF zero-cross outputs. Add them as sources once a way to raise a zero-cross without a motor is known, else cover them in the BLDC sensorless test
Not runP1unassigned
TC_TRGRTR_0002TRGRTR_REG_RWOpen issues
  • Open issue: Unimplemented address check passes whether or not a HardFault occurs. Change the code to require the HardFault so PSLVERR is proven
  • Open issue: Unimplemented address check starts at 0x4003C0F4. Extend it to cover 0x4003C09C to 0x4003C0F0
PASSP1unassigned
TC_TRGRTR_0003TRGRTR_DRB_ROUTINGOpen issues
  • Open issue: Define how CRM trg_in 0 to 2 (IOC, VOC, BOIC), TRG_OUT 15 to 17, are tested, which MCTRL enables can be set safely and on which board, then add them back as destinations
  • Open issue: Confirm SARADC_TRG_IN 0 to 2 start a conversion, which ADC setting selects each trigger and which internal channel gives a known result
  • Open issue: Confirm the 25 percent count tolerance for lf100k_clk and wdt_clk on silicon
  • Open issue: Confirm PWM2 and PWM3 TIN are capture inputs like PWM1 TIN
  • Open issue: Confirm CRM passes trg_in 3 to 5 through to trg_out 3 to 5 during the PWM0 dead zone, TRG_OUT 18 to 20 depend on it
  • Open issue: Gating of the PWM0 pins by TRG_OUT 21 to 26 needs a logic analyser and is covered by the BLDC test, here only the router side is checked through the feedback wires
Not runP1unassigned
TC_TRGRTR_0005TRGRTR_SOFT_RESETOpen issues
  • Open issue: Confirm whether CTRL1.SRST also clears STS and whether SRST clears itself, the test expects both
Not runP1unassigned
TC_TRGRTR_0006TRGRTR_LOW_POWER_WAKEUPOpen issues
  • Open issue: Confirm the APB0 clock stays on in SLEEP with CRM CGEN0 APB0_CGEN 2, the use-case document says APB clocks are gated off in SLEEP, sleep_prb_apb_clock depends on it
  • Open issue: Confirm GPT0 and GPT2 still wake the SoC with APB0_CGEN 2, the APB0 clock gated in DEEP SLEEP, deep_sleep_prb_no_clock, deep_sleep_drb_lf_clock and deep_sleep_drb_route_off depend on it
Not runP1unassigned
TC_TRGRTR_0007TRGRTR_SAFE_RECONFIGURATIONOpen issues
  • Open issue: Manual 17.8.5 step 2 says clear the status register, it should say clear only the STS bit of the route being changed, writing all ones loses pending events of routes that are running
  • Open issue: Find a way to stop one of the two PRB clocks while a route runs, to check the case the manual gives for setting GFB, AHB stops only while the CPU sleeps and gating APB0 also cuts CPU access to the TRGRTR, so it may not be reachable from software
Not runP2unassigned
TC_TRGRTR_0008TRGRTR_TIMINGOpen issues
  • Open issue: Confirm TRG_OUT 25, OE4, gates PWM0_HI_2 on the GPIO_5 pad so GPIO_5 follows TRG_OUT 25 while PWM0_HI_2 is held high
  • Open issue: Find whether GPIO_5 is driven low or left at high impedance while TRG_OUT 25 is low, if high impedance fit a 1 kohm pull-down on GPIO_5 and take the delay from the driven edge, the other edge then depends on the resistor and the pad load
  • Open issue: Confirm the Hall 0 pad, VO_R_Csense, accepts 0 to 3.3 V digital pulses from the signal generator and find its input threshold
  • Open issue: Confirm the VO_R_Csense and GPIO_5 pads are reachable for probing and wiring on VK001_RevA
  • Open issue: Decide how the measured values are entered into runtime.log for this manual test
Not runP2unassigned
TC_TRGRTR_0009TRGRTR_CRM_PROTECTIONOpen issues
  • Open issue: Add the buck-boost test board name to the boards list in config.yaml and add validation_board
  • Open issue: Define the probe points and wiring on the buck-boost test board for the fault stimulus and the switched rails
  • Open issue: Confirm the USB_VIN absolute maximum rating allows raising VIN above the 6 V overvoltage threshold with margin
  • Open issue: Find a safe way to draw more than 2.5 A from VIN for the IOC case
  • Open issue: Check whether CRM has a bit that forces IOC, VOC or BOIC without a real fault, which would make the PRB cases automatic
  • Open issue: Confirm CRM trg_out 0 to 2 assert as soon as the fault is detected, before the CRM automatic shutdown delay, otherwise the shutdown loop cannot be faster and the last pass criterion changes
Not runP1unassigned
TC_TRGRTR_0010TRGRTR_CONCURRENT_ROUTESOpen issues
  • Open issue: Confirm which GPT and PWM interrupt fires once per period in PWM mode, it is used to count the pulses
Not runP1unassigned

UART · 2 tests

Test caseNameCategoryReasonsLast run resultPriorityOwner
TC_UART_0015UART_HALF_DUPLEXPlan mismatch
  • Marked ready, but src/ has no code in the repo
Not runP1Jyeshta
TC_UART_0017UART_DEEPSLEEP_WAKEUPPlan mismatch
  • Marked ready, but src/ has no code in the repo
Not runP1Jyeshta

VAAK SoC · 1 test

Test caseNameCategoryReasonsLast run resultPriorityOwner
CoreMark Test for VAAK001UART_EXT_LOOPBACK_IOSET0Run not finished
  • Run did not finish: runtime.log has no TEST_RESULT lines
No verdict-unassigned

WDT · 2 tests

Test caseNameCategoryReasonsLast run resultPriorityOwner
TC_WDT_0002WDT_GEN_OF_INTERNAL_RESETRun not finished
  • Run did not finish: runtime.log has no TEST_RESULT lines
No verdict-unassigned
TC_WDT_0004WDT_LPM_WAKEUP_REQRun not finished
  • Run did not finish: runtime.log has no TEST_RESULT lines
No verdict-unassigned
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