VK001 Post-Si ValidationHW101x · silicon 1.0
Dashboard / SARADC

SARADC

4 test cases · SARADC · silicon 1.0 · generated 02-Nov-2026 14:11:07

PASS 1In development 3
No priority set1 of 4 passed · 3 not passed
Bench time (estimates)
TestsExecution (min – max)Setup (min – max)Total (min – max)Estimated
All tests4tbd-tbd0 of 4 tests
Not passed3tbd-tbd0 of 3 tests
Feature coverage · 3 features · 1 verified · 0 failing · 2 open
FeatureCovered byFeature status
Register Read Write
0001
PASS
Vin sweep test
0002
In development
CTRL.ADCEN read-back in continuous mode
00030003
In development

Test cases

4 of 4 shown
Priority
Status
Test caseName and test descriptionPriorityOwnerStatusLast runRun mode · setup · execution
TC_SARADC_0001
SARADC_REG_RW
  • Verify default register values after reset
  • Pattern write/read verification on RW registers
  • Read-only register validation for STS
  • Reserved bits write protection check across registers
  • Random read/write validation on RW registers
  • Invalid address access generates PSLVERR
  • Byte, half-word, and word access verification (hsize/pstrb)
  • Multi-reset sequence validation (C_RESET1 to C_RESET4)
-unassignedPASS
1/1
02-Sep-2026 19:15:44
-
-
execution tbd
TC_SARADC_0002
SARADC_REG_RW
  • Verify default register values after reset
  • Pattern write/read verification on RW registers
  • Read-only register validation for STS
  • Reserved bits write protection check across registers
  • Random read/write validation on RW registers
  • Invalid address access generates PSLVERR
  • Byte, half-word, and word access verification (hsize/pstrb)
  • Multi-reset sequence validation (C_RESET1 to C_RESET4)
-unassignedIn development
0/1
25-Aug-2026 15:35:07
-
-
execution tbd
TC_SARADC_0003
SARADC_ADCEN_READBACK
  • Slow the ADC (CRM FDIV0 PER0DIV=7, CTRL.AVGM=3), empty the FIFO with the ADC off
  • Enable with one full CTRL write - continuous mode, WML=1, CH7, ADCEN=1
  • Read CTRL 16 times (first read immediately after the enable), no other SARADC access in between
  • CTRL.RESCNT rising proves the ADC is converting; CTRL.ADCEN must read 1 in every read
-unassignedIn development-
-
-
execution tbd
TC_SARADC_0003
SARADC_ADCEN_READBACK
  • S1 Write CTRL with ADCEN=0 and read back (baseline)
  • S2 Write CTRL with ADCEN=1 (full write), prove conversions run (1000 EOCs), read CTRL.ADCEN while converting - expected 1
  • S3 Read CTRL and write the same value back (read-modify-write, no intended change) - conversions must continue
  • S4 Full CTRL write with ADCEN=1 again - conversions resume (informational)
  • S5 Re-write ADCEN=1 while converting - first samples after it (informational, restart behaviour)
-unassignedIn development-
-
-
execution tbd

TC_SARADC_0001 · SARADC_REG_RW

PASS1/1
owner unassignedexecution tbd
Last run02-Sep-2026 19:15:44
Silicon1.0
BoardVAAK001 RevA
Firmware commitunknown
Bugsnone
Filesreport · log

Test description

  • Verify default register values after reset
  • Pattern write/read verification on RW registers
  • Read-only register validation for STS
  • Reserved bits write protection check across registers
  • Random read/write validation on RW registers
  • Invalid address access generates PSLVERR
  • Byte, half-word, and word access verification (hsize/pstrb)
  • Multi-reset sequence validation (C_RESET1 to C_RESET4)

Pass / fail criteria

-

Hardware connection

  • The connections are made on the ATE board.
  • GPIO_3 (logger) ==> J1(21) ==> USB-to-UART(TX) ==> PC

Features and configuration

Register Read Write

1 result

TC_SARADC_0002 · SARADC_REG_RW

In development0/1
owner unassignedexecution tbd
Last run25-Aug-2026 15:35:07
Silicon1.0
BoardVAAK001 RevA
Firmware commitunknown
Bugsnone
Filesreport · log

Test description

  • Verify default register values after reset
  • Pattern write/read verification on RW registers
  • Read-only register validation for STS
  • Reserved bits write protection check across registers
  • Random read/write validation on RW registers
  • Invalid address access generates PSLVERR
  • Byte, half-word, and word access verification (hsize/pstrb)
  • Multi-reset sequence validation (C_RESET1 to C_RESET4)

Pass / fail criteria

-

Hardware connection

  • Not required

Features and configuration

Vin sweep test

1 result

TC_SARADC_0003 · SARADC_ADCEN_READBACK

In development
owner unassignedexecution tbd
Last runNot run yet
BoardVAAK001 RevA
Bugsnone

Test description

  • Slow the ADC (CRM FDIV0 PER0DIV=7, CTRL.AVGM=3), empty the FIFO with the ADC off
  • Enable with one full CTRL write - continuous mode, WML=1, CH7, ADCEN=1
  • Read CTRL 16 times (first read immediately after the enable), no other SARADC access in between
  • CTRL.RESCNT rising proves the ADC is converting; CTRL.ADCEN must read 1 in every read

Pass / fail criteria

-

Hardware connection

  • GPIO_6 -> fixed non-zero DC voltage (0.5 V to 1.4 V), same as func_Vin_sweep_test

Features and configuration

CTRL.ADCEN read-back in continuous mode

1 result

TC_SARADC_0003 · SARADC_ADCEN_READBACK

In development
owner unassignedexecution tbd
Last runNot run yet
BoardVAAK001 RevA
Bugsnone

Test description

  • S1 Write CTRL with ADCEN=0 and read back (baseline)
  • S2 Write CTRL with ADCEN=1 (full write), prove conversions run (1000 EOCs), read CTRL.ADCEN while converting - expected 1
  • S3 Read CTRL and write the same value back (read-modify-write, no intended change) - conversions must continue
  • S4 Full CTRL write with ADCEN=1 again - conversions resume (informational)
  • S5 Re-write ADCEN=1 while converting - first samples after it (informational, restart behaviour)

Pass / fail criteria

-

Hardware connection

  • GPIO_6 -> fixed non-zero DC voltage (0.5 V to 1.4 V), same as func_Vin_sweep_test

Features and configuration

CTRL.ADCEN read-back in continuous mode

1 result

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